公开(公告)号：US09985633B1

公开(公告)日：2018-05-29

申请号：US15263201

申请日：2016-09-12

申请人： Maxim Integrated Products, Inc.

发明人： Gabriel E. Tanase ,  Michael B. Francon

IPC分类号： H03K5/08 ,  H03K19/018

CPC分类号： H03K19/01806 ,  H03F3/3069 ,  H03F3/45071 ,  H03F2200/441 ,  H03K5/08 ,  H03K19/00307 ,  H03K19/017509 ,  H03M1/1295

摘要： A voltage clamping system includes: (a) a first electronic device connected to a first power source and having a signal output node, a voltage clamp high node, and a voltage clamp low node, wherein the voltage clamp high node and the voltage clamp low node are coupled to a second power source different than the first power source; and (b) a second electronic device powered by the second power source and having a signal input node coupled to the signal output node of the first electronic device. The signal output node of the first electronic device is passively clamped, with low distortion, approximately rail-to-rail with respect to the second power source such that the second electronic device is protected from damage due to excessive voltage levels.

公开(公告)号：US09764547B2

公开(公告)日：2017-09-19

申请号：US15299669

申请日：2016-10-21

申请人： Seiko Epson Corporation

发明人： Shuji Otsuka ,  Tadashi Kiyuna ,  Toshifumi Asanuma

IPC分类号： B41J2/045 ,  G11C19/00 ,  H03K19/018

CPC分类号： B41J2/04541 ,  B41J2/04573 ,  B41J2/04581 ,  B41J2/04586 ,  B41J2/04588 ,  G11C19/00 ,  H03K19/01806

摘要： A driving circuit for driving a capacitive load includes: an original drive signal generator that generates a plurality of original drive signals which includes a first original drive signal and a second original drive signal; a selection section that is capable of selecting one original drive signal from the plurality of original drive signals which includes the first original drive signal and the second original drive signal; a driver that generates a drive signal of voltages in accordance with the one original drive signal.

公开(公告)号：US09379709B2

公开(公告)日：2016-06-28

申请号：US14738472

申请日：2015-06-12

申请人： FINISAR CORPORATION

发明人： The'Linh Nguyen

IPC分类号： H03K19/0185 ,  H03K19/094 ,  H03K19/018 ,  H03K3/017 ,  H03K19/0175

CPC分类号： H03K19/018528 ,  H03K3/017 ,  H03K5/1565 ,  H03K19/017509 ,  H03K19/01806 ,  H03K19/018514

摘要： A circuit may include an input terminal configured to receive an input signal with a first voltage swing and an output terminal. The circuit may also include a first transistor, a second transistor, a third transistor, and a control circuit. The control circuit may be coupled to the input terminal, a gate terminal of the first transistor, and a gate terminal of the second transistor. The control circuit may be configured to adjust voltages provided to the gate terminals based on the input signal such that the first transistor conducts in response to the input signal being at a first logical level and the second transistor conducts in response to the input signal being at a second logical level to generate an output signal output on the output terminal. The second voltage swing of the output signal may be different from the first voltage swing of the input signal.

摘要翻译： 电路可以包括被配置为接收具有第一电压摆幅和输出端子的输入信号的输入端子。 电路还可以包括第一晶体管，第二晶体管，第三晶体管和控制电路。 控制电路可以耦合到输入端子，第一晶体管的栅极端子和第二晶体管的栅极端子。 控制电路可以被配置为基于输入信号来调整提供给栅极端子的电压，使得第一晶体管响应于第一逻辑电平而导通，并且第二晶体管响应于输入信号在 第二逻辑电平以在输出端子上产生输出信号。 输出信号的第二电压摆幅可以与输入信号的第一电压摆幅不同。

公开(公告)号：US20150006980A1

公开(公告)日：2015-01-01

申请号：US14273438

申请日：2014-05-08

申请人： UNIQUIFY, INC.

发明人： Mahesh Gopalan

IPC分类号： H04L1/20 ,  G06F11/07

CPC分类号： H04L7/0337 ,  G06F1/08 ,  G06F11/0763 ,  G06F11/0793 ,  H03K5/00 ,  H03K19/01806 ,  H04L1/205

摘要： A circuit and method for implementing a adaptive bit-leveling function in an integrated circuit interface is disclosed. During a calibration operation, a pre-loaded data bit pattern is continuously sent from a sending device and is continuously read from an external bus by a receiving device. A programmable delay line both advances and delays each individual data bit relative to a sampling point in time, and delay counts relative to a reference point in time are recorded for different sampled data bit values, enabling a delay to be determined that best samples a data bit at its midpoint. During the advancing and delaying of a data bit, jitter on the data bit signal may cause an ambiguity in the determination of the midpoint, and solutions are disclosed for detecting jitter and for resolving a midpoint for sampling a data bit even in the presence of the jitter.

摘要翻译： 公开了一种用于在集成电路接口中实现自适应位调平功能的电路和方法。 在校准操作期间，从发送设备连续地发送预加载的数据位模式，并且由接收设备从外部总线连续读取。 可编程延迟线都相对于采样点在时间上推进和延迟每个单独的数据位，并且针对不同的采样数据位值记录相对于参考点的延迟计数，使得能够确定最佳采样数据的延迟 位在它的中点。 在数据位的推进和延迟期间，数据位信号的抖动可能导致确定中点的模糊性，并且公开了用于检测抖动和解决用于采样数据位的中点的解决方案，即使存在 抖动。

公开(公告)号：US07893733B1

公开(公告)日：2011-02-22

申请号：US12502475

申请日：2009-07-14

申请人： Kien Beng Tan

发明人： Kien Beng Tan

IPC分类号： H03K3/00

CPC分类号： H03K5/003 ,  H03K19/01806

摘要： A voltage driver circuit includes a first transistor. The first transistor includes a control terminal, a first terminal, and a second terminal. The second transistor includes a control terminal, a first terminal, and a second terminal. A first current source configured to provide a first bias current to the control terminal of the first transistor. A second current source configured to provide a second bias current to the control terminal of the second transistor. The first resistance includes a first terminal connected to the control terminal of the first transistor. The second resistance includes a first terminal connected to the control terminal of the second transistor. A capacitance connects the second terminal of the first transistor with the control terminal of the second transistor. A ratio of the first bias current to the second bias current is approximately equal to a ratio of the second resistance to the first resistance.

摘要翻译： 电压驱动器电路包括第一晶体管。 第一晶体管包括控制端子，第一端子和第二端子。 第二晶体管包括控制端子，第一端子和第二端子。 第一电流源，被配置为向第一晶体管的控制端提供第一偏置电流。 第二电流源，被配置为向第二晶体管的控制端提供第二偏置电流。 第一电阻包括连接到第一晶体管的控制端的第一端。 第二电阻包括连接到第二晶体管的控制端的第一端。 电容将第一晶体管的第二端子与第二晶体管的控制端连接。 第一偏置电流与第二偏置电流的比率近似等于第二电阻与第一电阻的比值。

公开(公告)号：US20060139064A1

公开(公告)日：2006-06-29

申请号：US11297893

申请日：2005-12-09

申请人： Tong Zhou ,  Jia-Hui Tu

发明人： Tong Zhou ,  Jia-Hui Tu

IPC分类号： H03B1/00

CPC分类号： H03K19/01806

摘要： A drive circuit of a computer system is for driving a mode indicator. The computer system includes a first port and a second port. The mode indicator includes a first receiving end and a second receiving end. The drive circuit includes a first input end connected to the first port, a second input end connected to the second port, a first output end connected to the first receiving end, a second output end connected to the second receiving end, a power supply, a first transistor connected between the first input end and the power supply, and a second transistor connected between the second input end and the power supply. Collectors of the first and second transistors are separately connected to the first and second output ends. The mode indicator is dichromatic and has two LEDs emitting non-matching colored light

摘要翻译： 计算机系统的驱动电路用于驱动模式指示器。 计算机系统包括第一端口和第二端口。 模式指示器包括第一接收端和第二接收端。 驱动电路包括连接到第一端口的第一输入端，连接到第二端口的第二输入端，连接到第一接收端的第一输出端，​​连接到第二接收端的第二输出端，电源， 连接在第一输入端和电源之间的第一晶体管，以及连接在第二输入端和电源之间的第二晶体管。 第一和第二晶体管的集电极分别连接到第一和第二输出端。 模式指示器是二色的，并且具有发射不匹配的彩色光的两个LED

公开(公告)号：US20020036516A1

公开(公告)日：2002-03-28

申请号：US10001528

申请日：2001-10-24

发明人： John S. Petty

IPC分类号： H03K019/0175

CPC分类号： H03K19/01806 ,  Y10T307/305 ,  Y10T307/50 ,  Y10T307/516

摘要： Apparatus for electrically coupling a first digital device (408) and a second digital device (406) includes an interface circuit at the first digital device coupled at an interface node (230) to the second digital device. The interface circuit is configured to provide a first device supply voltage (Vcc2) to the interface node until a second device supply voltage (Vcc) at the interface node exceeds the first voltage. A data circuit (220) at the first digital device is coupled to the interface node. The data circuit is responsive to voltage on the interface node for providing digital logic signals at appropriate voltage levels to the second digital device.

公开(公告)号：US20010045845A1

公开(公告)日：2001-11-29

申请号：US09734686

申请日：2000-12-13

申请人： Fujitsu Limited

发明人： Umeo Oshio

IPC分类号： H03K019/0175

CPC分类号： H03K19/01806

摘要： Two LSIs are driven with different power supply voltages. An interface circuit which outputs a constant current corresponding to a logic signal to a first LSI and stopping the output of the constant current is provided in the first LSI. An interface circuit which generates a logic signal having a level conforming to the second LSI, based on the constant current, is provided in the second LSI.

摘要翻译： 两个LSI由不同的电源电压驱动。 在第一LSI中设置有向第一LSI输出对应于逻辑信号的恒定电流并停止恒定电流输出的接口电路。 在第二LSI中设置有基于恒定电流产生具有与第二LSI相符的电平的逻辑信号的接口电路。

公开(公告)号：US06212402B1

公开(公告)日：2001-04-03

申请号：US08746339

申请日：1996-11-08

申请人： Jan Ragnar Rubbmark ,  Göran Claes Pehrsson ,  Magnus Hans Hansson

发明人： Jan Ragnar Rubbmark ,  Göran Claes Pehrsson ,  Magnus Hans Hansson

IPC分类号： H04Q732

CPC分类号： H03K19/01843 ,  H03K19/01806

摘要： A system connector is provided to allow for the communication of digital signals between two devices functioning at different operating voltages. The connector allows for the interfacing of the high and low signal logic levels through the use of each devices own operating voltage without the need for complex signal conversion of voltage levels. The connector may be used to allow communication between mobile phones and their accessories. The system connector may be incorporated into an accessory or portable device allowing the signal level interfacing between the portable device and accessory. The system connector supplies a high-level or low-level digital signal to a first device operating at a first voltage in response to a corresponding high-level or low-level digital signal from a second device operating at a second voltage. In addition, the system connector may also provide a high-level or low-level digital signal from a second device operating at a second voltage in response to a corresponding high-level or low-level digital signal from the first device operating at the first voltage.

摘要翻译： 提供系统连接器以允许在不同工作电压下工作的两个设备之间的数字信号通信。 连接器允许通过使用每个设备自己的工作电压来连接高和低信号逻辑电平，而不需要电压电平的复杂信号转换。 连接器可用于允许移动电话及其附件之间的通信。 系统连接器可以并入到附件或便携式设备中，允许便携式设备和附件之间的信号电平接口。 系统连接器响应于来自在第二电压下工作的第二设备的相应的高电平或低电平数字信号，将高电平或低电平数字信号提供给以第一电压工作的第一设备。 此外，系统连接器还可以响应于来自第一设备的第一设备的对应的高电平或低电平数字信号，提供来自在第二电压下操作的第二设备的高电平或低电平数字信号 电压。

公开(公告)号：US5939922A

公开(公告)日：1999-08-17

申请号：US712416

申请日：1996-09-11

申请人： Toshiyuki Umeda

发明人： Toshiyuki Umeda

IPC分类号： H03K19/00 ,  H03K19/018 ,  H03K19/0185

CPC分类号： H03K19/001 ,  H03K19/01806

摘要： An input circuit includes a pair of common-base circuits having respective transistors including respective bases to which differential signals transmitted through a transmission line are input and constant current sources connected to the emitters of the transistors, and a level shift circuit for inputting, to the emitters of the common-base circuits, differential signals with anti-phase relation to the differential signals input to the bases of the common-base circuits. This input circuit has lower power consumption and can be used to match impedance.

摘要翻译： 输入电路包括一对共用基极电路，其具有各自的晶体管，该晶体管包括输入通过传输线传输的差分信号的各个基极和连接到晶体管的发射极的恒流源，以及电平移位电路， 共基极电路的发射极，与输入到公共基极电路的基极的差分信号具有反相关的差分信号。 该输入电路具有较低的功耗，可用于匹配阻抗。