公开(公告)号：US11279212B2

公开(公告)日：2022-03-22

申请号：US16747826

申请日：2020-01-21

申请人： Jia Hui Wang

发明人： Jia Hui Wang

IPC分类号： B60J7/14 ,  B60J7/16 ,  B60P7/02

摘要： A pickup truck bed cover includes foldable horizontal sections retained on a mounting frame by left and right latches attached under the sections. The latches mounting plates, left and right locks, and left and right operating mechanisms. The operating mechanisms are connected to the locks to pull the locks into disengagement with the mounting frame allowing the sections to be folded. Connecting members connect the operating mechanisms. When a handle of one of the operating mechanism is being twisted, both the left and right locking blocks are simultaneously retract to disengage with the mounting frame. When the handle is released, the left and right locks extend to engage the mounting frame. The rotation of the handles may be coupled to the locks by sliding cylinders having spiral surfaces engaged by inside protrusions in the handles. Springs inside the handles bias the sliding cylinders apart to engage the locks.

公开(公告)号：US08368673B2

公开(公告)日：2013-02-05

申请号：US12241367

申请日：2008-09-30

申请人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Ching-Chung Lee

发明人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Ching-Chung Lee

IPC分类号： G09G5/00 ,  H03F3/45

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/0291

摘要： An output buffer and a source driver for a display panel are provided. The output buffer includes a differential input stage, a bias current source, a feedback module, and an output stage. The differential input stage has a first input terminal and a second input terminal receiving a first input signal and a second input signal respectively, and a first output terminal. The bias module provides a bias current to the differential input stage. The output stage has a second output terminal coupled to the first input terminal for providing an output current to the second output terminal based on a signal of the first output terminal. The feedback module adjusts the bias current and the output current based on the first input signal and the second input signal. The output buffer has ability of switching the output voltage to be low level and high level in high-speed.

摘要翻译： 提供了用于显示面板的输出缓冲器和源驱动器。 输出缓冲器包括差分输入级，偏置电流源，反馈模块和输出级。 差分输入级具有分别接收第一输入信号和第二输入信号的第一输入端和第二输入端，以及第一输出端。 偏置模块向差分输入级提供偏置电流。 输出级具有耦合到第一输入端的第二输出端，用于基于第一输出端的信号向第二输出端提供输出电流。 反馈模块基于第一输入信号和第二输入信号调整偏置电流和输出电流。 输出缓冲器具有将输出电压切换为低电平和高电平的能力。

公开(公告)号：US20100079431A1

公开(公告)日：2010-04-01

申请号：US12241367

申请日：2008-09-30

申请人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Ching-Chung Lee

发明人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Ching-Chung Lee

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G2310/0291

摘要： An output buffer and a source driver for a display panel are provided. The output buffer includes a differential input stage, a bias current source, a feedback module, and an output stage. The differential input stage has a first input terminal and a second input terminal receiving a first input signal and a second input signal respectively, and a first output terminal. The bias module provides a bias current to the differential input stage. The output stage has a second output terminal coupled to the first input terminal for providing an output current to the second output terminal based on a signal of the first output terminal. The feedback module adjusts the bias current and the output current based on the first input signal and the second input signal. The output buffer has ability of switching the output voltage to be low level and high level in high-speed.

摘要翻译： 提供了用于显示面板的输出缓冲器和源驱动器。 输出缓冲器包括差分输入级，偏置电流源，反馈模块和输出级。 差分输入级具有分别接收第一输入信号和第二输入信号的第一输入端和第二输入端，以及第一输出端。 偏置模块向差分输入级提供偏置电流。 输出级具有耦合到第一输入端的第二输出端，用于基于第一输出端的信号向第二输出端提供输出电流。 反馈模块基于第一输入信号和第二输入信号调整偏置电流和输出电流。 输出缓冲器具有将输出电压切换为低电平和高电平的能力。

公开(公告)号：US08717349B2

公开(公告)日：2014-05-06

申请号：US12549636

申请日：2009-08-28

申请人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Chin-Tien Chang ,  Ying-Lieh Chen

发明人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Chin-Tien Chang ,  Ying-Lieh Chen

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G2320/0223

摘要： A source driver adapted to drive a display panel is provided herein. The source driver includes a first output buffer, a detection module and a conversion module. The first output buffer enhances a first pixel signal and thereby outputs a first enhanced pixel signal. The detection module detects a rise time of the first enhanced pixel signal. The conversion module adjusts a driving capability of the first output buffer in response to the rise time for adjusting a slew rate of the first output buffer. Therefore, the first output buffer in the source driver can dynamically and automatically adjusts the slew rate of the first output buffer through a feedback mechanism composed of the detection module and the conversion module.

摘要翻译： 本文提供了适于驱动显示面板的源驱动器。 源驱动器包括第一输出缓冲器，检测模块和转换模块。 第一输出缓冲器增强第一像素信号，从而输出第一增强像素信号。 检测模块检测第一增强像素信号的上升时间。 转换模块响应于用于调整第一输出缓冲器的转换速率的上升时间来调整第一输出缓冲器的驱动能力。 因此，源驱动器中的第一个输出缓冲器可以通过由检测模块和转换模块组成的反馈机制来动态和自动地调整第一输出缓冲器的转换速率。

公开(公告)号：US08188955B2

公开(公告)日：2012-05-29

申请号：US12258957

申请日：2008-10-27

申请人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Jing-Chuan Qiu ,  Chen-Yu Wang

发明人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Jing-Chuan Qiu ,  Chen-Yu Wang

IPC分类号： H03F3/45

CPC分类号： G09G3/3688

摘要： A source driving circuit adapted to drive a display panel is provided herein. The source driving circuit includes a first output buffer and a second output buffer responsible for enhancing signals with different polarities respectively. As for the first output buffer, the first output buffer includes a first differential input stage, a first output stage and a second output stage. The first output stage includes a first level adjustment circuit and a first self-bias providing circuit. The first level adjustment circuit provides a first level voltage according to input signals received by the first differential input stage, such that the second output stage thereby provides a first charge current and a second charge current to output a first output signal based on the first level voltage. The first self-bias providing circuit provides a first biased voltage associated with one input signal to control the first level adjustment circuit to operate.

摘要翻译： 本文提供了适于驱动显示面板的源极驱动电路。 源极驱动电路包括分别负责增强具有不同极性的信号的第一输出缓冲器和第二输出缓冲器。 对于第一输出缓冲器，第一输出缓冲器包括第一差分输入级，第一输出级和第二输出级。 第一输出级包括第一电平调节电路和第一自偏压提供电路。 第一电平调节电路根据由第一差分输入级接收的输入信号提供第一电平电压，使得第二输出级由此提供第一充电电流和第二充电电流，以基于第一电平输出第一输出信号 电压。 第一自偏压提供电路提供与一个输入信号相关联的第一偏置电压以控制第一电平调节电路进行操作。

公开(公告)号：US20130234760A1

公开(公告)日：2013-09-12

申请号：US13413309

申请日：2012-03-06

申请人： Jia-Hui Wang ,  Hung-Yu Huang

发明人： Jia-Hui Wang ,  Hung-Yu Huang

IPC分类号： H03B1/00

CPC分类号： G11C7/1057

摘要： An output buffer including a P-type transistor, an N-type transistor, a first comparison unit and a second comparison unit is provided. The P-type transistor has a first source, a first gate and a first drain. The first source receives a system voltage, and the first drain outputs an output voltage. The N-type transistor has a second drain, a second gate and a second source. The second drain is coupled to the first drain, and the second source receives a ground voltage. The first comparison unit and the second comparison unit respectively output a high voltage or a low voltage to the first gate and the second gate according to a comparison result of an input voltage and the output voltage, and respectively regulate a first tail current flowing into the first comparison unit and a second tail current flowing from the second comparison unit accordingly.

摘要翻译： 提供了包括P型晶体管，N型晶体管，第一比较单元和第二比较单元的输出缓冲器。 P型晶体管具有第一源极，第一栅极和第一漏极。 第一个源接收系统电压，第一个漏极输出一个输出电压。 N型晶体管具有第二漏极，第二栅极和第二源极。 第二漏极耦合到第一漏极，第二源极接收地电压。 第一比较单元和第二比较单元根据输入电压和输出电压的比较结果分别向第一栅极和第二栅极输出高电压或低电压，并分别调节流入 第一比较单元和第二尾电流相应地从第二比较单元流出。

公开(公告)号：US20110032240A1

公开(公告)日：2011-02-10

申请号：US12536050

申请日：2009-08-05

申请人： Jia-Hui Wang ,  Chien-Hung Tsai ,  Ying-Lieh Chen ,  Chin-Tien Chang

发明人： Jia-Hui Wang ,  Chien-Hung Tsai ,  Ying-Lieh Chen ,  Chin-Tien Chang

IPC分类号： G09G5/00 ,  H03F3/16 ,  H03L5/00

CPC分类号： H03F3/3022 ,  G09G3/2092 ,  G09G2300/0426 ,  G09G2330/021 ,  G09G2360/18 ,  H03F1/0205

摘要： A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption.

摘要翻译： 提供了具有降低功耗的缓冲电路。 输出缓冲电路包括第一和第二放大器电路。 第一放大器电路包括耦合在第一电源电压和低于第一电源电压的第二电源电压之间的第一输入级和第一输出级，以及辅助放电单元，被配置为提供从第一输出节点 在第一放大器电路的放电操作期间到第一中间电源电压。 第二放大器电路包括耦合在第一电源电压和第二电源电压之间的第二输入级和第二输出级，以及辅助充电单元，被配置为提供从第二中间电源电压流向第二输出节点的充电电流 在第二放大器电路的充电操作期间。 第一和第二放大器电路可以具有降低的输出电压范围，从而降低总功耗。

公开(公告)号：US20100171531A1

公开(公告)日：2010-07-08

申请号：US12350653

申请日：2009-01-08

申请人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Jing-Chuan Qiu ,  Chen-Yu Wang

发明人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Jing-Chuan Qiu ,  Chen-Yu Wang

IPC分类号： H03B29/00

CPC分类号： H03K19/018528

摘要： An output buffer including a first differential input stage, a primary output stage, and a secondary output stage is provided herein. The first differential input stage respectively receives a first and a second input signals via a first and a second input terminals. The primary output stage includes a first and a second output stages. The first output stage provides at least one first level voltage according to the first and the second input signals, and the second output stage controlled by the first level voltage drives an output terminal of the output buffer to a target level. The secondary output stage includes a comparator and a third output stage. The comparator compares the induced currents in the first differential input stage, and thereby generates a control voltage. The third output stage controlled by the control voltage drives the output terminal of the output buffer to the target level.

摘要翻译： 提供了包括第一差分输入级，初级输出级和次级输出级的输出缓冲器。 第一差分输入级经由第一和第二输入端分别接收第一和第二输入信号。 主输出级包括第一和第二输出级。 第一输出级根据第一和第二输入信号提供至少一个第一电平电压，并且由第一电平电压控制的第二输出级将输出缓冲器的输出端驱动到目标电平。 次级输出级包括比较器和第三输出级。 比较器比较第一差分输入级中的感应电流，从而产生控制电压。 由控制电压控制的第三输出级将输出缓冲器的输出端驱动到目标电平。

公开(公告)号：US20100103152A1

公开(公告)日：2010-04-29

申请号：US12258957

申请日：2008-10-27

申请人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Jing-Chuan Qiu ,  Chen-Yu Wang

发明人： Chien-Hung Tsai ,  Jia-Hui Wang ,  Jing-Chuan Qiu ,  Chen-Yu Wang

IPC分类号： G09G5/00

CPC分类号： G09G3/3688

摘要： A source driving circuit adapted to drive a display panel is provided herein. The source driving circuit includes a first output buffer and a second output buffer responsible for enhancing signals with different polarities respectively. As for the first output buffer, the first output buffer includes a first differential input stage, a first output stage and a second output stage. The first output stage includes a first level adjustment circuit and a first self-bias providing circuit. The first level adjustment circuit provides a first level voltage according to input signals received by the first differential input stage, such that the second output stage thereby provides a first charge current and a second charge current to output a first output signal based on the first level voltage. The first self-bias providing circuit provides a first biased voltage associated with one input signal to control the first level adjustment circuit to operate.

摘要翻译： 本文提供了适于驱动显示面板的源极驱动电路。 源极驱动电路包括分别负责增强具有不同极性的信号的第一输出缓冲器和第二输出缓冲器。 对于第一输出缓冲器，第一输出缓冲器包括第一差分输入级，第一输出级和第二输出级。 第一输出级包括第一电平调节电路和第一自偏压提供电路。 第一电平调节电路根据由第一差分输入级接收的输入信号提供第一电平电压，使得第二输出级由此提供第一充电电流和第二充电电流，以基于第一电平输出第一输出信号 电压。 第一自偏压提供电路提供与一个输入信号相关联的第一偏置电压以控制第一电平调节电路进行操作。

公开(公告)号：US08508515B2

公开(公告)日：2013-08-13

申请号：US12536050

申请日：2009-08-05

申请人： Jia-Hui Wang ,  Chien-Hung Tsai ,  Ying-Lieh Chen ,  Chin-Tien Chang

发明人： Jia-Hui Wang ,  Chien-Hung Tsai ,  Ying-Lieh Chen ,  Chin-Tien Chang

IPC分类号： G06F3/038

CPC分类号： H03F3/3022 ,  G09G3/2092 ,  G09G2300/0426 ,  G09G2330/021 ,  G09G2360/18 ,  H03F1/0205

摘要： A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit. The first and second amplifier circuits can have reduced output voltage ranges and hence reduced total power consumption.

摘要翻译： 提供了具有降低的功耗的缓冲电路。 输出缓冲电路包括第一和第二放大器电路。 第一放大器电路包括耦合在第一电源电压和低于第一电源电压的第二电源电压之间的第一输入级和第一输出级，以及辅助放电单元，被配置为提供从第一输出节点 在第一放大器电路的放电操作期间达到第一中间电源电压。 第二放大器电路包括耦合在第一电源电压和第二电源电压之间的第二输入级和第二输出级，以及辅助充电单元，被配置为提供从第二中间电源电压流向第二输出节点的充电电流 在第二放大器电路的充电操作期间。 第一和第二放大器电路可以具有降低的输出电压范围，从而降低总功耗。