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    Code size reduction method through multiple load/store instructions
    1.
    发明授权
    Code size reduction method through multiple load/store instructions 失效
    通过多个加载/存储指令进行代码缩小方法

    公开(公告)号：US07493463B2

    公开(公告)日：2009-02-17

    申请号：US11189793

    申请日：2005-07-27

    申请人： Yun-Heung Paek ,  Jun-seo Lee ,  Jin-oo Joung ,  Min-wook Ahn ,  Jun-sik Choi ,  Doo-san Cho

    发明人： Yun-Heung Paek ,  Jun-seo Lee ,  Jin-oo Joung ,  Min-wook Ahn ,  Jun-sik Choi ,  Doo-san Cho

    IPC分类号： G06F13/00

    CPC分类号： G06F8/4434

    摘要： A method to transfer a plurality of data stored in a memory using one instruction. In a memory including at least two regions to which the addresses are assigned respectively, data are allocated to the addresses in sequence, and the allocated data are transferred using one instruction. At least one block is generated, which transfers data using one instruction, and it is instructed to include the data in the at least one block. The data in the block are linked with each other, and the number of paths linking two data is calculated with respect to the at least one block. The data are linked using shortest paths in consideration of the number of the linking paths, and the data are allocated by the addresses using the shortest paths.

    摘要翻译： 一种使用一条指令传送存储在存储器中的多个数据的方法。 在包括分配给地址的至少两个区域的存储器中，按顺序将数据分配给地址，并且使用一条指令传送分配的数据。 生成至少一个块，其使用一个指令传送数据，并且指示将数据包括在至少一个块中。 块中的数据彼此链接，并且相对于至少一个块计算链接两个数据的路径的数量。 考虑到链接路径的数量，使用最短路径链接数据，并且通过使用最短路径的地址来分配数据。

    Hardware device for executing conditional instruction out-of-order fetch and execution method thereof
    2.
    发明申请
    Hardware device for executing conditional instruction out-of-order fetch and execution method thereof 审中-公开
    用于执行条件指令无序读取的硬件设备及其执行方法

    公开(公告)号：US20060095733A1

    公开(公告)日：2006-05-04

    申请号：US11219797

    申请日：2005-09-07

    申请人： Yong-surk Lee ,  Ha-young Jeong ,  Nam-guk Kim ,  Jin-oo Joung ,  Tae-ho Jang ,  Dae-ung Kim

    发明人： Yong-surk Lee ,  Ha-young Jeong ,  Nam-guk Kim ,  Jin-oo Joung ,  Tae-ho Jang ,  Dae-ung Kim

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30072

    摘要： A hardware device for executing conditional instructions out-of-order and the execution method. An architecture is provided, enabling the hardware device such as a processor supporting the conditional instruction and a computer system to execute the instruction out-of-order. To this end, a conditional execution buffer is provided, and a register of a destination operand of the conditional instruction is renamed to another register. Hence, the hardware device using the conditional instruction can carry out the out-of-order execution, and the execution speed of the hardware device can be greatly improved.

    摘要翻译： 用于执行无序条件指令和执行方法的硬件设备。 提供了一种架构，使诸如支持条件指令的处理器等硬件设备和计算机系统执行无序指令。 为此，提供了条件执行缓冲器，并将条件指令的目的地操作数的寄存器重命名为另一个寄存器。 因此，使用条件指令的硬件设备可以执行无序执行，并且可以大大提高硬件设备的执行速度。