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107 条记录 (耗时 0.02 秒)

    DC offset removal for a magnetic field sensor
    2.
    发明授权
    DC offset removal for a magnetic field sensor 有权
    用于磁场传感器的直流偏移去除

    公开(公告)号：US08269491B2

    公开(公告)日：2012-09-18

    申请号：US12038119

    申请日：2008-02-27

    申请人： John Cummings ,  William P. Taylor ,  David J. Haas

    发明人： John Cummings ,  William P. Taylor ,  David J. Haas

    IPC分类号： G01R33/09 ,  G01N27/72

    CPC分类号： G01R33/09 ,  G01R15/202 ,  G01R15/205 ,  G01R15/207 ,  G01R33/0023 ,  G01R33/0029 ,  G01R33/0035

    摘要： Presented is a sensor that includes a magnetoresistive (MR) sensing device to sense a magnetic field and to produce an AC signal voltage proportional to the sensed magnetic field. The sensor also includes circuitry, coupled to the MR sensing device, to remove DC offset from the AC signal voltage. The DC offset may be related to the hysteresis characteristics of the MR sensing device. To remove DC offset, the circuitry may obtain an averaged DC offset and subtract the averaged DC offset from the AC signal voltage to produce a sensor output signal.

    摘要翻译： 提出了一种传感器，其包括用于感测磁场并产生与所感测的磁场成比例的AC信号电压的磁阻（MR）感测装置。 传感器还包括耦合到MR感测装置的电路，以从AC信号电压去除DC偏移。 DC偏移可能与MR感测装置的滞后特性有关。 为了消除DC偏移，电路可以获得平均DC偏移，并从AC信号电压中减去平均的DC偏移量，以产生传感器输出信号。

    Design Structure for switching digital circuit clock net driver without losing clock pulses
    3.
    发明授权
    Design Structure for switching digital circuit clock net driver without losing clock pulses 有权
    用于切换数字电路时钟网络驱动器而不会丢失时钟脉冲的设计结构

    公开(公告)号：US08086977B2

    公开(公告)日：2011-12-27

    申请号：US12192272

    申请日：2008-08-15

    申请人： Jethro C. Law ,  Kirk Edward Morrow ,  John Cummings Schiff ,  Glen Arthur Wiedemeier

    发明人： Jethro C. Law ,  Kirk Edward Morrow ,  John Cummings Schiff ,  Glen Arthur Wiedemeier

    IPC分类号： G06F17/50

    CPC分类号： G06F1/08

    摘要： A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.

    摘要翻译： 提出了一种不损失时钟脉冲来切换数字电路时钟网络驱动器的系统和方法。 器件使用无毛刺时钟选择逻辑，其包括边沿检测器，以根据器件电路的性能要求选择时钟信号以提供给器件电路。 当第一时钟信号和第二时钟信号的上升沿对齐时，边缘检测器瞬时地将用于将时钟选择信号时钟的时钟切换信号脉冲发送到多路复用器。 结果，当时钟选择信号为高电平时，器件等待直到时钟沿对齐才能切换时钟信号。

    Showerhead
    4.
    发明申请
    Showerhead 审中-公开
    淋浴头

    公开(公告)号：US20110290916A1

    公开(公告)日：2011-12-01

    申请号：US12912302

    申请日：2010-10-26

    申请人： Stephen John Cummings ,  David George Stone

    发明人： Stephen John Cummings ,  David George Stone

    IPC分类号： B05B1/00

    CPC分类号： B05B15/654 ,  B05B1/18 ,  B05B1/265 ,  B05B1/3006 ,  B05B15/656

    摘要： A showerhead (10) with an outlet defined by an inwardly facing first sharp edge (44) surrounded by an outwardly extending first surface (46). The first surface (46) is angled in the opposite direction to that of water (Sr, Se) leaving the outlet.

    摘要翻译： 一个具有由向内延伸的第一表面（46）围绕的面向内的第一锋利边缘（44）限定的出口的喷头（10）。 第一表面（46）与离开出口的水（Sr，Se）相反的方向倾斜。

    System and method for switching digital circuit clock net driver without losing clock pulses
    8.
    发明授权
    System and method for switching digital circuit clock net driver without losing clock pulses 有权
    用于切换数字电路时钟网络驱动器而不会丢失时钟脉冲的系统和方法

    公开(公告)号：US07752480B2

    公开(公告)日：2010-07-06

    申请号：US11465639

    申请日：2006-08-18

    申请人： Jethro C. Law ,  Kirk Edward Morrow ,  John Cummings Schiff ,  Glen Arthur Wiedemeier

    发明人： Jethro C. Law ,  Kirk Edward Morrow ,  John Cummings Schiff ,  Glen Arthur Wiedemeier

    IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F5/06

    CPC分类号： G06F1/08

    摘要： A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.

    摘要翻译： 提出了一种不损失时钟脉冲来切换数字电路时钟网络驱动器的系统和方法。 器件使用无毛刺时钟选择逻辑，其包括边沿检测器，以根据器件电路的性能要求选择时钟信号以提供给器件电路。 当第一时钟信号和第二时钟信号的上升沿对齐时，边缘检测器瞬时地将用于将时钟选择信号时钟的时钟切换信号脉冲发送到多路复用器。 结果，当时钟选择信号为高电平时，器件等待直到时钟沿对齐才能切换时钟信号。