Output circuit for 3V/5V clock chip duty cycle adjustments
    1.
    发明授权
    Output circuit for 3V/5V clock chip duty cycle adjustments 失效
    输出电路用于3V / 5V时钟芯片占空比调整

    公开(公告)号:US5856753A

    公开(公告)日:1999-01-05

    申请号:US624925

    申请日:1996-03-29

    IPC分类号: H03K5/02 H03K5/13

    CPC分类号: H03K5/023

    摘要: The present invention provides an analog biased pre-driver and pad as well as a duty cycle adjustment cell prior to the pre-driver and pad. The pre-driver and pad may operate in either a 3 volt mode, a 5 volt mode or any voltage in between depending only on the power supply voltage present. No production configuration or post-production configuration is required. The present invention utilizes a special bias circuit to reduce the Vcc, temperature and other processing variations. A duty cycle cell produces a range of duty cycles when the circuit is operating between a 3 volt and 5 volt range.

    摘要翻译: 本发明在预驱动器和焊盘之前提供模拟偏置预驱动器和焊盘以及占空比调整单元。 预驱动器和焊盘可以在3伏模式,5伏模式或其间的任何电压下工作,仅取决于存在的电源电压。 不需要生产配置或后期制作配置。 本发明利用特殊的偏置电路来降低Vcc,温度和其它处理变化。 当电路工作在3伏和5伏范围之间时,占空比单元产生占空比的范围。

    Digitally compensated voltage controlled oscillator
    2.
    发明授权
    Digitally compensated voltage controlled oscillator 有权
    数字补偿压控振荡器

    公开(公告)号:US06563390B1

    公开(公告)日:2003-05-13

    申请号:US09753063

    申请日:2000-12-29

    申请人: John W. Kizziar

    发明人: John W. Kizziar

    IPC分类号: H03B532

    摘要: An apparatus comprising a digitally controlled oscillator and a frequency tuning array. The digitally controlled oscillator may be configured to finely tune an output signal having a frequency in response to a digital signal. The frequency tuning array may be configured to generate the digital signal.

    摘要翻译: 一种包括数字控制振荡器和频率调谐阵列的装置。 数字控制振荡器可以被配置为微调响应于数字信号的具有频率的输出信号。 频率调谐阵列可以被配置为产生数字信号。