公开(公告)号：US4685077A

公开(公告)日：1987-08-04

申请号：US692348

申请日：1985-01-17

申请人： Johnson Loo

发明人： Johnson Loo

IPC分类号： G06F7/52

CPC分类号： G06F7/5272 ,  G06F2207/382

摘要： There is described a data processing apparatus with a binary multiplication capability. The apparatus has an arithmetic and logic unit (ALU) and a operand register. The operand register is divided into two portions, the first of which can be shifted while the second is loaded in parallel. For multiplication, the first portion is used to hold a multiplier and to receive the least significant bits of the result, while the second portion receives the most significant bits of the result. The invention avoids the need for a separate shift register to hold the multiplier. The described apparatus also has a look-ahead facility, for selecting the next bit of the multiplier ahead of its requirement, so that it is immediately available when required.

摘要翻译： 描述了具有二进制乘法能力的数据处理装置。 该装置具有算术和逻辑单元（ALU）和操作数寄存器。 操作数寄存器分为两部分，第一个可以移位，而第二个并行加载。 对于乘法，第一部分用于保持乘法器并接收结果的最低有效位，而第二部分接收结果的最高有效位。 本发明避免了需要单独的移位寄存器来保持乘法器。 所描述的装置还具有先行设备，用于在其要求之前选择乘法器的下一位，使得在需要时立即可用。

公开(公告)号：US4628512A

公开(公告)日：1986-12-09

申请号：US690726

申请日：1985-01-11

申请人： Johnson Loo

发明人： Johnson Loo

IPC分类号： G06F12/16 ,  G06F11/00 ,  G11C7/00 ,  G11C7/02 ,  G11C8/00 ,  G06F11/10

CPC分类号： G06F11/0763 ,  G11C8/00

摘要： In a data storage apparatus, memory chips are arranged in groups, each group having an address bus which is connected to the address inputs of all the chips in that group. Each address bus is terminated at both ends by circuits which perform the dual function of suppressing reflections and checking the addresses.Because reflections are suppressed, the time taken to address the store is reduced. One of the termination circuits in each group is arranged to compare the address on the bus with that on the bus in the adjacent group; the other circuit compares the address with a predetermined value.

摘要翻译： 在数据存储装置中，存储器芯片被分组布置，每组具有连接到该组中所有芯片的地址输入的地址总线。 每个地址总线由执行抑制反射和检查地址的双重功能的电路两端终止。 由于反射被抑制，因此减少了解决商店的时间。 每个组中的一个终端电路被布置成将总线上的地址与相邻组中的总线上的地址进行比较; 另一个电路将地址与预定值进行比较。

公开(公告)号：US4639866A

公开(公告)日：1987-01-27

申请号：US690727

申请日：1985-01-11

申请人： Johnson Loo

发明人： Johnson Loo

IPC分类号： G06F9/38

CPC分类号： G06F9/3875 ,  G06F9/3824

摘要： A pipelined data processor is described, which obeys a sequence of instructions each with a read phase in which an operand is read from a memory, an execute phase in which an operation is performed by an execution unit, and a write phase in which a result is written into the memory. The phases of successive instructions are overlapped, and each instruction is stepped on to its next phase at the end of each clock beat. Each clock beat is divided into a write sub-beat followed by two read sub-beats. The write address for each instruction is stored in a write address register and is compared with each read or write address applied to the memory. When these addresses match, the output of the execution unit is either written into the memory (if the match occurs during a write sub-beat) or fed back to the execution unit as an operand (if the match occurs during a read sub-beat). In the latter case, the operand is made available to the next instruction without having to pass through the memory, and this overcomes the problem of a read/write clash, where one instruction requires to read an operand which has not yet been written by the preceding instruction.

摘要翻译： 描述了流水线数据处理器，其遵守每个具有从存储器读取操作数的读取阶段的指令序列，执行单元执行操作的执行阶段和其中结果的写入阶段 被写入内存。 连续指令的相位重叠，并且每个指令在每个时钟节拍结束时被踩到其下一个相位。 每个时钟拍子被分成一个写子拍子，然后是两个读取的次拍子。 每个指令的写入地址存储在写入地址寄存器中，并与应用于存储器的每个读取或写入地址进行比较。 当这些地址匹配时，执行单元的输出被写入存储器（如果匹配发生在写入子拍子期间）或者被反馈到执行单元作为操作数（如果匹配发生在读取子拍子期间 ）。 在后一种情况下，操作数可用于下一条指令而不必通过存储器，并且这克服了读/写冲突的问题，其中一个指令需要读取还没有被写入的操作数 上一条指示。