公开(公告)号：US20160124708A1

公开(公告)日：2016-05-05

申请号：US14878562

申请日：2015-10-08

申请人： ARM Limited

发明人： Andreas Due ENGH-HALSTVEDT ,  Edvard FIELDING

IPC分类号： G06F5/01

CPC分类号： G06F7/506 ,  G06F7/5272 ,  G06F7/535 ,  H03M7/24

摘要： An apparatus, method and program are provided for calculating a result value to a required precision of a repeating iterative sum, wherein the repeating iterative sum comprises multiple iterations of an addition using an input value. Addition is performed in a single iteration of addition as a sum operation using overlapping portions of the input value and a shifted version of the input value, wherein the shifted version of the input value has a partial overlap with the input value. At least one result portion is produced by incrementing an input derived from the input value using the output from the sum operation and the result value is constructed using the at least one result portion to give the result value to the required precision. The repeating iterative sum is thereby flattened into a flattened calculation which requires only a single iteration of addition using the input value, thus facilitating the calculation of the result value of the repeating iterative sum.

摘要翻译： 提供了一种用于将结果值计算为重复迭代和的所需精度的装置，方法和程序，其中所述重复迭代和包括使用输入值的加法的多次迭代。 在加法的单次迭代中，作为使用输入值的重叠部分和输入值的移位版本的求和运算进行加法，其中输入值的移位版本与输入值具有部分重叠。 至少一个结果部分通过使用和操作的输出递增从输入值导出的输入而产生，并且使用至少一个结果部分构造结果值，以将结果值提供给所需精度。 因此，重复迭代和被平坦化为仅需要使用输入值的单次迭代迭代的扁平化计算，因此有助于计算重复迭代和的结果值。

公开(公告)号：US09032009B2

公开(公告)日：2015-05-12

申请号：US13794739

申请日：2013-03-11

申请人： Rohit Goyal ,  Amit Kumar Dey

发明人： Rohit Goyal ,  Amit Kumar Dey

IPC分类号： G06F7/533 ,  G06F7/527 ,  G06F7/74

CPC分类号： G06F7/5272 ,  G06F7/74

摘要： A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

摘要翻译： 用于将第一和第二二进制值相乘的乘法器电路包括第一逻辑电路，优先级编码器，移位器电路和累加器。 第一个逻辑电路接收第一个二进制值和一个乘数修饰符，并且基于乘数修饰符来修改第一个二进制值。 乘数修改器由优先级编码器生成。 优先级编码器还生成指示修改的第一二进制值中最高有效集位置的位置的位置二进制值。 移位器电路从优先编码器和第二二进制值接收位置二进制值并产生中间结果。 累加器累积一个或多个中间结果，并产生作为第一和第二二进制值的乘积的最终产品。

公开(公告)号：US20140253214A1

公开(公告)日：2014-09-11

申请号：US13794739

申请日：2013-03-11

申请人： Rohit Goyal ,  Amit Kumar Dey

发明人： Rohit Goyal ,  Amit Kumar Dey

IPC分类号： G06F7/44

CPC分类号： G06F7/5272 ,  G06F7/74

摘要： A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

摘要翻译： 用于将第一和第二二进制值相乘的乘法器电路包括第一逻辑电路，优先级编码器，移位器电路和累加器。 第一个逻辑电路接收第一个二进制值和一个乘数修饰符，并且基于乘数修饰符来修改第一个二进制值。 乘数修改器由优先级编码器生成。 优先级编码器还生成指示修改的第一二进制值中最高有效集位置的位置的位置二进制值。 移位器电路从优先编码器和第二二进制值接收位置二进制值并产生中间结果。 累加器累积一个或多个中间结果，并产生作为第一和第二二进制值的乘积的最终产品。

公开(公告)号：US20060158218A1

公开(公告)日：2006-07-20

申请号：US10545643

申请日：2004-02-12

申请人： Katarzyna Leijten-Nowak

发明人： Katarzyna Leijten-Nowak

IPC分类号： H03K19/177

CPC分类号： G06F7/503 ,  G06F7/5272 ,  G11C16/10 ,  H03K19/1737 ,  H03K19/17728

摘要： An electronic circuit has a programmable logic cell with a plurality of programmable logic units that are capable of being configured to operate in a multi-bit operand mode and a multiplexing mode. The programmable logic units are coupled in parallel between an input circuit and an output circuit. In a multi-bit operand processing mode the input circuit is configured to supply logic input signals from different ones of the logic inputs to the programmable logic units. The programmable logic units are coupled to successive positions along a carry chain at least in the multi-bit operand mode, so as to process carry signals from the carry chain. An output circuit passes outputs from the programmable logic units in parallel in the multi-bit operand mode. The programmable logic units have look-up tables which share the same configuration bits. The programmable logic units can also have multiplexers for passing one of the received input signals when configured to operate in a multiplexing mode of operation.

摘要翻译： 电子电路具有可编程逻辑单元，其具有多个可编程逻辑单元，其能够被配置为以多位操作数模式和复用模式操作。 可编程逻辑单元在输入电路和输出电路之间并联耦合。 在多位操作数处理模式中，输入电路被配置为将逻辑输入信号从不同的逻辑输入提供给可编程逻辑单元。 可编程逻辑单元至少在多位操作数模式下沿着进位链耦合到连续位置，以便处理来自进位链的进位信号。 输出电路在多位操作数模式下并行传送可编程逻辑单元的输出。 可编程逻辑单元具有共享相同配置位的查找表。 可编程逻辑单元还可以具有多路复用器，用于当被配置为在多路复用操作模式下操作时，使所接收的输入信号之一通过。

公开(公告)号：US4970675A

公开(公告)日：1990-11-13

申请号：US310172

申请日：1989-02-15

申请人： Philippe Gallay ,  Eric Depret

发明人： Philippe Gallay ,  Eric Depret

IPC分类号： G06F7/50 ,  G06F7/52 ,  G06F7/72

CPC分类号： G06F7/5272 ,  G06F7/5095 ,  G06F7/722 ,  G06F7/49931 ,  G06F7/723

摘要： A multiplier for two binary values, X and Y, comprising a very high number (q) of bits, wherein memories storing the numbers X and Y and a result register MR are provided, X being expressed as the sequence of bits (x.sub.q-1 . . . x.sub.j . . . x.sub.0), uses the algorithm consisting in sequentially carrying out from j=q-1 to j=0 the additions 2R+x.sub.j Y and each time entering the result in the result memory (MR). In this multiplier the adders are grouped into n blocks of m bits (with n.times.m=q), m being chosen so that the carry transfer time into a block is lower than a clock period. Each block comprises a first and a second line of elementary adders forming the cells (C.sub.1 to C.sub.m+1) associated with each pair of bits to be added. This multiplier is more particularly adapted for carrying out the operations XYmodN and X.sup.S modN.

摘要翻译： 两个二进制值的乘法器X和Y包括非常高数量的（q）位，其中存储存储数字X和Y的存储器和结果寄存器MR被提供，X被表示为比特序列（xq-1 使用从j = q-1到j = 0顺序执行的算法，加法2R + xjY，每次在结果存储器（MR）中输入结果）。 在该乘法器中，加法器被分组成n个m位（n×m = q），m被选择，使得进入块的进位传送时间低于时钟周期。 每个块包括形成与要添加的每对比特相关联的小区（C1至Cm + 1）的基本加法器的第一和第二行。 该乘法器特别适用于执行XYmodN和XSmodN的操作。

公开(公告)号：US4685077A

公开(公告)日：1987-08-04

申请号：US692348

申请日：1985-01-17

申请人： Johnson Loo

发明人： Johnson Loo

IPC分类号： G06F7/52

CPC分类号： G06F7/5272 ,  G06F2207/382

摘要： There is described a data processing apparatus with a binary multiplication capability. The apparatus has an arithmetic and logic unit (ALU) and a operand register. The operand register is divided into two portions, the first of which can be shifted while the second is loaded in parallel. For multiplication, the first portion is used to hold a multiplier and to receive the least significant bits of the result, while the second portion receives the most significant bits of the result. The invention avoids the need for a separate shift register to hold the multiplier. The described apparatus also has a look-ahead facility, for selecting the next bit of the multiplier ahead of its requirement, so that it is immediately available when required.

摘要翻译： 描述了具有二进制乘法能力的数据处理装置。 该装置具有算术和逻辑单元（ALU）和操作数寄存器。 操作数寄存器分为两部分，第一个可以移位，而第二个并行加载。 对于乘法，第一部分用于保持乘法器并接收结果的最低有效位，而第二部分接收结果的最高有效位。 本发明避免了需要单独的移位寄存器来保持乘法器。 所描述的装置还具有先行设备，用于在其要求之前选择乘法器的下一位，使得在需要时立即可用。

公开(公告)号：US4228518A

公开(公告)日：1980-10-14

申请号：US945736

申请日：1978-09-25

申请人： George P. Chamberlin

发明人： George P. Chamberlin

IPC分类号： G06F7/508 ,  G06F7/52 ,  G06F7/533 ,  G06F15/78 ,  G06F7/54

CPC分类号： G06F7/5272 ,  G06F7/535 ,  G06F2207/5352

摘要： A microprocessor having the capability of performing either a multiply or divide operation from a single instruction for each operation is provided. Much of the standard circuitry of a microprocessor is used along with a multiply/divide cycle counter, logic circuitry, and a shift network separate from the arithmetic logic unit. The microprocessor has the capability of performing unsigned integer multiplication and division. A shift and add algorithm is used for multiplication while for division a non-restoring divide algorithm is used.

摘要翻译： 提供了具有从每个操作的单个指令执行乘法或除法运算的能力的微处理器。 微处理器的大部分标准电路与乘法/除法周期计数器，逻辑电路和与算术逻辑单元分离的移位网络一起使用。 微处理器具有执行无符号整数乘法和除法的能力。 使用移位和加法算法进行乘法，而对于除法使用非恢复分割算法。

公开(公告)号：US3737638A

公开(公告)日：1973-06-05

申请号：US3737638D

申请日：1972-07-18

申请人： IBM

发明人： ESTEBAN D

IPC分类号： G06F7/52 ,  G06F7/54

CPC分类号： G06F7/5272 ,  G06F2207/3832

摘要： A serial para lel multiplication device in which the digits of the multiplicand are coded in two''s complement and in which the digits of the multiplier are coded in two''s complement modified by inverting the highest ranking digit and appending another digit of predetermined value as the last digit, the appended digit having the same rank as the lowest ranking digit. The devie produces a series of partial products, each partial product being formed by logically combining the inverse of the ith multiplier digit with each multiplicand digit. As a consequence, each partial product digit assumes one value if the correspondingly ranking multiplicand and ith multiplier digits match and another value if they mismatch. The partial product is then corrected by adding to it the value of the ith digit.

摘要翻译： 一种串行派生乘法装置，其中被乘数的数字以二进制补码编码，并且其中乘数的数字被编码为二进制补码，通过反转最高排名数字并附加预定值的另一数字作为最后一位， 附加数字与最低排名数字具有相同的排名。 该产品产生一系列部分产品，每个部分产品通过逻辑组合第i个乘法器​​数字的倒数与每个被乘数形成。 因此，如果相应的排名被乘数和第i个乘数匹配，则每个部分乘积数字假定为一个值，如果它们不匹配则假定为另一个值。 然后通过向其中加上第i位的值来校正部分乘积。

公开(公告)号：US3646522A

公开(公告)日：1972-02-29

申请号：US3646522D

申请日：1969-08-15

申请人： INTERDATA INC

发明人： FURMAN ARTHUR R ,  JONES RICHARD ,  MORELAND CHARLES ,  NESTLE ELLIOT

IPC分类号： G06F7/52 ,  G06F9/22 ,  G06F9/26 ,  G06F9/14

CPC分类号： G06F7/5272 ,  G06F7/535 ,  G06F9/226 ,  G06F9/261 ,  G06F2207/5353

摘要： A processor system having a main memory to store user instructions and a read only memory which contains microroutines to emulate the user instructions. A user''s instruction is fetched from the main memory and placed in an instruction register, a separate decode read only memory holds the individual starting address for the appropriate microroutine utilized in a current user instruction. The operation code of the user''s instruction is applied from the instruction register to the decode read only memory for obtaining the starting address of a predetermined microroutine. Further, multiplication and division are performed according to a unique set of microroutines to significantly decrease processor operating time.

公开(公告)号：US3557355A

公开(公告)日：1971-01-19

申请号：US3557355D

申请日：1967-07-14

申请人： GEN ELECTRIC

发明人： PORTER MARION G

IPC分类号： G06F7/52 ,  G06F7/39

CPC分类号： G06F7/5272

摘要： A data processing system including an arithmetic unit in communication with a data processing unit provides the capacity of performing instruction execution operations upon data supplied thereto by the processing unit. The system further includes means for detecting the completion of an algorithm execution, in particular the completion of a multiplication algorithm.