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公开(公告)号：US20100146369A1
公开(公告)日：2010-06-10
申请号：US12694829
申请日：2010-01-27
CPC分类号： H03M13/03 , G06F11/1028 , G11C7/1006 , G11C2207/104
摘要： Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.
摘要翻译： 公开了用于最小化与可单独访问的存储器件相关联的软错误的影响的技术。 作为示例，在由纠错码保护的存储器件的存储器阵列中组织列的方法包括通过使与存储器线相关联的存储器位之间的物理距离最大化来最大化纠错码的距离的步骤 在由纠错码保护的列内。 其他软错误保护技术可以包括使用前馈纠错码或使用存储器操作（例如，读或写操作）抑制和重试方法。
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公开(公告)号：US08949685B2
公开(公告)日：2015-02-03
申请号：US12694829
申请日：2010-01-27
CPC分类号： H03M13/03 , G06F11/1028 , G11C7/1006 , G11C2207/104
摘要： Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.
摘要翻译： 公开了用于最小化与可单独访问的存储器件相关联的软错误的影响的技术。 作为示例，在由纠错码保护的存储器件的存储器阵列中组织列的方法包括通过使与存储器线相关联的存储器位之间的物理距离最大化来最大化纠错码的距离的步骤 在由纠错码保护的列内。 其他软错误保护技术可以包括使用前馈纠错码或使用存储器操作（例如，读或写操作）抑制和重试方法。
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3.发明申请PHASE AND FREQUENCY DETECTOR WITH OUTPUT PROPORTIONAL TO FREQUENCY DIFFERENCE 有权相位和频率检测器具有输出比例为频率差异公开(公告)号：US20110063003A1
公开(公告)日：2011-03-17
申请号：US12813828
申请日：2010-06-11
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/093 , H03L7/1077 , H03L7/1976
摘要： Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.
摘要翻译： 公开了相位和频率检测器和技术。 例如，装置包括用于接收第一和第二时钟信号的第一电路，以及用于产生指示第一和第二时钟信号之间的相位差的至少一个信号。 该装置还包括第二电路，用于接收由第一电路产生的至少一个信号，并响应于该至少一个接收信号，产生至少一个输出信号，其中与该至少一个输出信号相关的频率为 与第一和第二时钟信号之间的频率差成比例。
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4.发明授权公开(公告)号：US08222936B2
公开(公告)日：2012-07-17
申请号：US12813828
申请日：2010-06-11
IPC分类号： H03L7/06
CPC分类号： H03L7/089 , H03L7/093 , H03L7/1077 , H03L7/1976
摘要： Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.
摘要翻译： 公开了相位和频率检测器和技术。 例如，装置包括用于接收第一和第二时钟信号的第一电路，以及用于产生指示第一和第二时钟信号之间的相位差的至少一个信号。 该装置还包括第二电路，用于接收由第一电路产生的至少一个信号，并响应于该至少一个接收信号，产生至少一个输出信号，其中与该至少一个输出信号相关的频率为 与第一和第二时钟信号之间的频率差成比例。
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公开(公告)号：US07721182B2
公开(公告)日：2010-05-18
申请号：US11140133
申请日：2005-05-27
IPC分类号： G11C29/00
CPC分类号： H03M13/03 , G06F11/1028 , G11C7/1006 , G11C2207/104
摘要： Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach.
摘要翻译： 公开了用于最小化与可单独访问的存储器件相关联的软错误的影响的技术。 作为示例，在由纠错码保护的存储器件的存储器阵列中组织列的方法包括通过使与存储器线相关联的存储器位之间的物理距离最大化来最大化纠错码的距离的步骤 在由纠错码保护的列内。 其他软错误保护技术可以包括使用前馈纠错码或使用存储器操作（例如，读或写操作）抑制和重试方法。
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6.发明授权Method and apparatus for reducing latency in a digital signal processing device 失效用于减少数字信号处理装置中的等待时间的方法和装置公开(公告)号：US07107301B2
公开(公告)日：2006-09-12
申请号：US10095206
申请日：2002-03-11
CPC分类号： H03H17/0223 , H03H17/0241 , H03H17/06 , H03K2005/00078
摘要： A digital signal processing device for processing an input signal includes delay generation circuitry and processing circuitry. The delay generation circuitry receives the input signal and includes a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith. The delay generation circuitry includes a zero delay signal path and at least one nonzero delay signal path associated therewith. The processing circuitry is operatively configured to: (i) define a first subset of signal paths through the delay generation circuitry, the first subset including the zero delay signal path, and at least a second subset of signal paths through the delay generation circuitry, the second subset including one or more nonzero delay signal paths; (ii) remove an idle delay from all signal paths in the second subset, such that a shortest nonzero delay signal path in the second subset becomes a zero delay signal path; and (iii) incorporate the idle delay with the processing circuitry.
摘要翻译： 一种用于处理输入信号的数字信号处理装置包括延迟产生电路和处理电路。 延迟产生电路接收输入信号并且包括可操作地耦合在一起的多个延迟级，每个延迟级具有与之相关联的预定时间延迟。 延迟产生电路包括零延迟信号路径和与其相关联的至少一个非零延迟信号路径。 处理电路可操作地配置为：（i）通过延迟产生电路定义信号路径的第一子集，第一子集包括零延迟信号路径，以及通过延迟产生电路的信号路径的至少第二子集， 第二子集包括一个或多个非零延迟信号路径; （ii）从所述第二子集中的所有信号路径去除空闲延迟，使得所述第二子集中的最短非零延迟信号路径变为零延迟信号路径; 和（iii）将空闲延迟与处理电路相结合。
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7.发明授权Method and apparatus for comparing two binary numbers with a power-of-two threshold 失效用于将两个二进制数与两个阈值进行比较的方法和装置公开(公告)号：US06795842B2
公开(公告)日：2004-09-21
申请号：US09749081
申请日：2000-12-27
申请人： José A. Tierno
发明人： José A. Tierno
IPC分类号： G06F702
CPC分类号： G06F7/026
摘要： Methods and apparatus for comparing two binary numbers with a power-of-two threshold are provided in accordance with the present invention. In one embodiment, a method for comparing two binary numbers with a power-of-two threshold includes the steps of generating new relations, namely, much_greater_than (ggi) and equal_to (nqi), based at least in part on generate (gt) and propagate (eq) signals created for each bit of the binary numbers to be compared, and applying recursion in order to reduce the set of input signals at successive recursive nodes by a predetermined number. By omitting a pre-addition operation, the present invention eliminates the use of exclusive-OR logic gates, thus significantly reducing system cost and delay.
摘要翻译： 根据本发明提供了用于比较两个二进制数与二权阈值的方法和装置。 在一个实施例中，用于将两个二进制数与二权值进行比较的方法包括以下步骤：至少部分地基于generate（gt）和...生成新的关系，即，most_greater_than（ggi）和等于（nqi） 对要比较的二进制数的每个位创建的传播（eq）信号，并应用递归，以便将连续递归节点处的输入信号的集合减少预定数量。 通过省略预加法操作，本发明消除了异或逻辑门的使用，从而显着降低系统成本和延迟。
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