公开(公告)号：US20090210843A1

公开(公告)日：2009-08-20

申请号：US12032517

申请日：2008-02-15

申请人： Christopher J. Berry ,  Jose Luis Ponters Correia Neves ,  Lawrence David Curley ,  Patrick James Meaney ,  Travis Wellington Pouarz ,  William J. Scarpero, JR.

发明人： Christopher J. Berry ,  Jose Luis Ponters Correia Neves ,  Lawrence David Curley ,  Patrick James Meaney ,  Travis Wellington Pouarz ,  William J. Scarpero, JR.

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62

摘要： The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.

摘要翻译： 在集成芯片设计中布置时钟控制分配网络的平面图的过程被简化，并且提高了创建分段网络的效率。 在Cadence Viewer中查看芯片平面图的图片时，不是在HDL中手动创建分段网络，也可以将其作为网络描述表，在Cadence环境中运行的自动化方法使用算法方法来最大限度地提高利用率 分段锁存器，消除不必要的电源和区域使用。 通过使用算法到达的分段解决方案直接更新物理布局来最大化效率。