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1.发明授权Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy 有权优化具有多层次结构的集成电路中的扫描链的方法公开(公告)号：US07987400B2
公开(公告)日：2011-07-26
申请号：US12035500
申请日：2008-02-22
CPC分类号： G01R31/318536
摘要： A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.
摘要翻译： 一种用于优化集成电路中具有多层次层次结构的扫描链的方法，可以解决无限链和树桩，并分开所有其他链和树桩。 通过将链包围的区域和残端的起始点和终点分成由多个网格框组成的网格，并且将网格框确定为网格框连接路由以访问所有网格框，来优化无限链和树桩 的起始点和终点之间的网格框通过运行路由算法的计算机。 优化的所有其他链和树桩被随机地分配给一个树桩，一个可以通过该树桩物理达到的链，并根据附加链中的锁存数，其物理位置和锁存数量向该残基添加一个附加链 已分配
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2.发明授权Video encoding method, system and computer program product for optimizing center of picture quality 失效视频编码方法，系统和计算机程序产品，用于优化图像质量中心
公开(公告)号：US5920359A
公开(公告)日：1999-07-06
申请号：US858831
申请日：1997-05-19
摘要： A digital video encoding method, apparatus and computer program product are described with enhanced encoding of a picture having a plurality of macroblocks. The approach is to partition the picture into at least two regions and then to set or adjust at least one encoding parameter for each macroblock of the picture based upon the region of the picture within which the macroblock is located. As one specific implementation, the picture is partitioned into a center region and at least one outer region and the at least one encoding parameter is set to enhance picture quality in the center region at the expense of picture quality in the at least one outer region. The encoding parameter can, for example, be a motion estimation parameter, a quantization value, or a target bits per macroblock.
摘要翻译： 使用具有多个宏块的图像的增强编码来描述数字视频编码方法，装置和计算机程序产品。 该方法是将图像划分为至少两个区域，然后基于宏块所在的图像的区域来设置或调整图像的每个宏块的至少一个编码参数。 作为一个具体实施方案，图像被划分为中心区域和至少一个外部区域，并且设置至少一个编码参数以牺牲至少一个外部区域中的图像质量的费用来增强中心区域中的图像质量。 编码参数可以例如是运动估计参数，量化值或每个宏块的目标比特。
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3.发明申请Method for Optimizing Scan Chains in an Integrated Circuit that has Multiple Levels of Hierarchy 有权用于优化具有多层次结构的集成电路中的扫描链的方法公开(公告)号：US20090217115A1
公开(公告)日：2009-08-27
申请号：US12035500
申请日：2008-02-22
IPC分类号： G01R31/3181
CPC分类号： G01R31/318536
摘要： A method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy addresses unlimited chains and stumps and separately all other chains and stumps. Unlimited chains and stumps are optimized by dividing an area encompassed by the chains and by a start point and an end point of the stump into a grid comprised of a plurality of grid boxes, and determining a grid box to grid box connectivity route to access all of the grid boxes between the start point and the end point by means of a computer running a routing algorithm. All other chains and stumps are optimized randomly assigning to a stump a chain that can be physically reached by that stump and adding an additional chain to that stump based on the number of latches in the additional chain, its physical location, and the number of latches already assigned.
摘要翻译： 一种用于优化集成电路中具有多层次层次结构的扫描链的方法，可以解决无限链和树桩，并分开所有其他链和树桩。 通过将链包围的区域和残端的起始点和终点分成由多个网格框组成的网格，并且将网格框确定为网格框连接路由以访问所有网格框，来优化无限链和树桩 的起始点和终点之间的网格框通过运行路由算法的计算机。 优化的所有其他链和树桩被随机地分配给一个树桩，一个可以通过该树桩物理达到的链，并根据附加链中的锁存数，其物理位置和锁存数量向该残基添加一个附加链 已分配
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4.发明授权Method of automating creation of a clock control distribution network in an integrated circuit floorplan 有权在集成电路平面图中自动创建时钟控制分配网络的方法公开(公告)号：US07979838B2
公开(公告)日：2011-07-12
申请号：US12032517
申请日：2008-02-15
申请人： Christopher J. Berry , Jose Luis Pontes Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, Jr.
发明人： Christopher J. Berry , Jose Luis Pontes Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, Jr.
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.
摘要翻译： 在集成芯片设计中布置时钟控制分配网络的平面图的过程被简化，并且提高了创建分段网络的效率。 在Cadence Viewer中查看芯片平面图的图片时，不是在HDL中手动创建分段网络，也可以将其作为网络描述表，在Cadence环境中运行的自动化方法使用算法方法来最大限度地利用 分段锁存器，消除不必要的电源和区域使用。 通过使用算法到达的分段解决方案直接更新物理布局来最大化效率。
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5.发明申请Method of Automating Creation of a Clock Control Distribution Network in an Integrated Circuit Floorplan 有权在集成电路平面图中自动创建时钟控制分配网络的方法公开(公告)号：US20090210843A1
公开(公告)日：2009-08-20
申请号：US12032517
申请日：2008-02-15
申请人： Christopher J. Berry , Jose Luis Ponters Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, JR.
发明人： Christopher J. Berry , Jose Luis Ponters Correia Neves , Lawrence David Curley , Patrick James Meaney , Travis Wellington Pouarz , William J. Scarpero, JR.
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62
摘要： The process of laying out a floorplan for a clock control distribution network in an integrated chip design is simplified and the efficiency of a staging network created is improved. Rather than manually create the staging network in HDL or as a network description table while looking at a picture of the chip floorplan in a Cadence Viewer, an automated method which runs in the Cadence environment uses an algorithmic approach to the problem of maximizing the utilization of staging latches, eliminating unnecessary power and area usage. Efficiency is maximized by updating the Physical Layout directly with the staging solution arrived at by the algorithm.
摘要翻译： 在集成芯片设计中布置时钟控制分配网络的平面图的过程被简化，并且提高了创建分段网络的效率。 在Cadence Viewer中查看芯片平面图的图片时，不是在HDL中手动创建分段网络，也可以将其作为网络描述表，在Cadence环境中运行的自动化方法使用算法方法来最大限度地提高利用率 分段锁存器，消除不必要的电源和区域使用。 通过使用算法到达的分段解决方案直接更新物理布局来最大化效率。
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