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1.发明授权Accelerated simulation and verification of a system under test (SUT) using cache and replacement management tables 有权使用缓存和替换管理表加速对被测系统（SUT）的仿真和验证公开(公告)号：US07756695B2
公开(公告)日：2010-07-13
申请号：US11464122
申请日：2006-08-11
CPC分类号： G06F17/5027
摘要： A cache replacement system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking is provided. The system includes a Cell Broadband Engine Architecture (CBEA) compliant system implementing Replacement Management Tables in an accelerated simulation environment. The RMTs control cache replacement and allow the software to direct entries with specific address ranges at a particular subset of the cache. The RMTs further allow for locking data in the cache and are utilized to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets, which, when the microprocessor system being tested is correctly designed, generates identical and verifiable data and cache states in each of the different sets of the cache.
摘要翻译： 提供了一种缓存替换系统，用于通过启用增强的缓存数据和状态检查来扩展加速仿真的调试功能。 该系统包括在加速模拟环境中实施替换管理表的Cell Broadband Engine Architecture（CBEA）兼容系统。 RMT控制高速缓存替换，并允许软件在缓存的特定子集处指定具有特定地址范围的条目。 RMT还允许在高速缓存中锁定数据，并且用于通过指导已知在特定集合中仅使用一次的数据来防止重写高速缓存中的数据。 在加速模拟环境中使用锁定机制，用户能够运行代码集，当正确设计被测试的微处理器系统时，可以在每个不同的高速缓存集中的每一个中生成相同和可验证的数据和高速缓存状态。
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2.发明申请ACCELERATED SIMULATION AND VERIFICATION OF A SYSTEM UNDER TEST (SUT) USING CACHE AND REPLACEMENT MANAGEMENT TABLES 有权使用高速缓存和替换管理表进行测试（SUT）的系统的加速模拟和验证公开(公告)号：US20080126068A1
公开(公告)日：2008-05-29
申请号：US11464122
申请日：2006-08-11
IPC分类号： G06F9/455
CPC分类号： G06F17/5027
摘要： A cache replacement system for extending the debugging capabilities of accelerated simulation by enabling enhanced cache data and state checking is provided. The system includes a Cell Broadband Engine Architecture (CBEA) compliant system implementing Replacement Management Tables in an accelerated simulation environment. The RMTs control cache replacement and allow the software to direct entries with specific address ranges at a particular subset of the cache. The RMTs further allow for locking data in the cache and are utilized to prevent overwriting data in the cache by directing data that is known to be used only once at a particular set. Using the locking mechanism in an accelerated simulation environment, a user is able to run code sets, which, when the microprocessor system being tested is correctly designed, generates identical and verifiable data and cache states in each of the different sets of the cache.
摘要翻译： 提供了一种缓存替换系统，用于通过启用增强的缓存数据和状态检查来扩展加速仿真的调试功能。 该系统包括在加速模拟环境中实施替换管理表的Cell Broadband Engine Architecture（CBEA）兼容系统。 RMT控制高速缓存替换，并允许软件在缓存的特定子集处指定具有特定地址范围的条目。 RMT还允许在高速缓存中锁定数据，并且用于通过指导已知在特定集合中仅使用一次的数据来防止重写高速缓存中的数据。 在加速模拟环境中使用锁定机制，用户能够运行代码集，当正确设计被测试的微处理器系统时，可以在每个不同的高速缓存集中的每一个中生成相同和可验证的数据和高速缓存状态。
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