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公开(公告)号:US08031010B1
公开(公告)日:2011-10-04
申请号:US12566481
申请日:2009-09-24
CPC分类号: H03L7/26 , G04F5/145 , H03L1/022 , H03L7/0805
摘要: The present invention is a Chip Scale Atomic Clock (CSAC)-enabled Time and Frequency Standard (CTFS) architecture. The CTFS architecture includes a microcontroller, a Time Compensated Crystal Oscillator (TCCO) circuit which is connected to the microcontroller, and a Chip Scale Atomic Clock (CSAC) which is connected to the microcontroller. The microcontroller is configured for selectively causing the CTFS to provide a TCCO circuit-based output frequency when the CTFS has not locked to a predetermined atomic resonance, and is further configured for causing the CTFS to provide a CSAC-based output frequency when the CTFS has locked to a predetermined atomic resonance.
摘要翻译: 本发明是一种基于芯片级原子钟(CSAC)的时间和频率标准(CTFS)架构。 CTFS架构包括微控制器,连接到微控制器的时间补偿晶体振荡器(TCCO)电路和连接到微控制器的芯片级原子钟(CSAC)。 微控制器被配置为当CTFS未锁定到预定的原子共振时,选择性地使CTFS提供基于TCCO电路的输出频率,并且还被配置为当CTFS具有基于CSAC的输出频率时,CTFS提供基于CSAC的输出频率 锁定到预定的原子共振。