公开(公告)号：US20110064081A1

公开(公告)日：2011-03-17

申请号：US12947535

申请日：2010-11-16

Applicant: William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

Inventor： William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

IPC: H04L12/56

CPC classification number: H04L45/60 ,  H04L45/00 ,  H04L49/602

Abstract: Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.

Abstract translation: 用于路由包括用于第二网络协议的报头信息的第一网络协议的有效载荷的技术包括传送分组。 在电路块中，确定用于第一网络协议的第一类型和用于第二网络协议的第二类型。 电路块存储指示第一类型和第二类型的唯一组合的分类。 通用处理器根据分类路由数据包。 处理器时钟周期将被保存，用于确定类型。 此外，基于分类，处理器可以存储用于使标题相对于高速缓存行对准的偏移值。 电路块可以存储偏移值移位的数据包。 处理器然后可以从存储器检索单个高速缓存线以接收标题，从而节省高速缓存的多余的加载和弹出。

公开(公告)号：US08599855B2

公开(公告)日：2013-12-03

申请号：US12947535

申请日：2010-11-16

Applicant: William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

Inventor： William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

IPC: H04L12/28

CPC classification number: H04L45/60 ,  H04L45/00 ,  H04L49/602

Abstract: Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.

Abstract translation: 用于路由包括用于第二网络协议的报头信息的第一网络协议的有效载荷的技术包括传送分组。 在电路块中，确定用于第一网络协议的第一类型和用于第二网络协议的第二类型。 电路块存储指示第一类型和第二类型的唯一组合的分类。 通用处理器根据分类路由数据包。 处理器时钟周期将被保存，用于确定类型。 此外，基于分类，处理器可以存储用于使标题相对于高速缓存行对准的偏移值。 电路块可以存储偏移值移位的数据包。 处理器然后可以从存储器检索单个高速缓存线以接收标题，从而节省高速缓存的多余的加载和弹出。

公开(公告)号：US20060104268A1

公开(公告)日：2006-05-18

申请号：US10988754

申请日：2004-11-15

Applicant: William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

Inventor： William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

IPC: H04L12/56 ,  H04L12/28

CPC classification number: H04L45/60 ,  H04L45/00 ,  H04L49/602

Abstract: Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.

Abstract translation: 用于路由包括用于第二网络协议的报头信息的第一网络协议的有效载荷的技术包括传送分组。 在电路块中，确定用于第一网络协议的第一类型和用于第二网络协议的第二类型。 电路块存储指示第一类型和第二类型的唯一组合的分类。 通用处理器根据分类路由数据包。 处理器时钟周期将被保存，用于确定类型。 此外，基于分类，处理器可以存储用于使标题相对于高速缓存行对准的偏移值。 电路块可以存储偏移值移位的数据包。 处理器然后可以从存储器检索单个高速缓存线以接收标题，从而节省高速缓存的多余的加载和弹出。

公开(公告)号：US20140060050A1

公开(公告)日：2014-03-06

申请号：US14008848

申请日：2012-03-30

Applicant: Bhaskara Kosamana ,  Joydeep Chowdhury ,  Arunachalam Chettiyar ,  Saravanaram T. ,  Rakesh Govindasamy

Inventor： Bhaskara Kosamana ,  Joydeep Chowdhury ,  Arunachalam Chettiyar ,  Saravanaram T. ,  Rakesh Govindasamy

IPC: F03G6/06 ,  F03G6/00

CPC classification number: F03G6/067 ,  F01K25/08 ,  F03G6/003 ,  F03G6/005 ,  F03G6/065 ,  Y02E10/46

Abstract: Systems and methods for transforming solar energy into mechanical and/or electrical energy by using an ORC fluid in an ORC cycle configuration. The ORC cycle configuration includes a heat source that vaporizes the ORC fluid and an expander that expands the vaporized ORC fluid to produce the energy.

Abstract translation: 通过使用ORC循环配置中的ORC流体将太阳能转化为机械和/或电能的系统和方法。 ORC循环配置包括使ORC流体蒸发的热源和使蒸发的ORC流体膨胀以产生能量的膨胀器。

公开(公告)号：US07848332B2

公开(公告)日：2010-12-07

申请号：US10988754

申请日：2004-11-15

Applicant: William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

Inventor： William Lee ,  Michael Wright ,  Joydeep Chowdhury ,  Sriram Haridas ,  Martin Hughes

IPC: H04L12/56

CPC classification number: H04L45/60 ,  H04L45/00 ,  H04L49/602

Abstract: Techniques for routing a payload of a first network protocol, which includes header information for a second network protocol, include communicating a packet. In a circuit block, a first type for the first network protocol and a second type for the second network protocol are determined. The circuit block stores a classification that indicates a unique combination of the first type and the second type. A general purpose processor routes the packet based on the classification. Processor clock cycles are saved that would be consumed in determining the types. Furthermore, based on the classification, the processor can store an offset value for aligning the header relative to a cache line. The circuit block can store the packet shifted by the offset value. The processor can then retrieve from memory a single cache line to receive the header, thereby saving excess loading and ejecting of cache.

Abstract translation: 用于路由包括用于第二网络协议的报头信息的第一网络协议的有效载荷的技术包括传送分组。 在电路块中，确定用于第一网络协议的第一类型和用于第二网络协议的第二类型。 电路块存储指示第一类型和第二类型的唯一组合的分类。 通用处理器根据分类路由数据包。 处理器时钟周期将被保存，用于确定类型。 此外，基于分类，处理器可以存储用于使标题相对于高速缓存行对准的偏移值。 电路块可以存储偏移值移位的数据包。 处理器然后可以从存储器检索单个高速缓存线以接收标题，从而节省高速缓存的多余的加载和弹出。

公开(公告)号：US07555582B2

公开(公告)日：2009-06-30

申请号：US11640527

申请日：2006-12-15

Applicant: Grady David Lambert ,  Joydeep Chowdhury ,  Carson Stuart ,  Ryan McDaniel

Inventor： Grady David Lambert ,  Joydeep Chowdhury ,  Carson Stuart ,  Ryan McDaniel

IPC: G06F13/12 ,  G06F13/38

CPC classification number: G11C7/1006 ,  G11C5/005 ,  G11C5/04

Abstract: Portable USB memory modules or devices and methods for using such devices are disclosed herein. In one embodiment, a portable memory module can include a housing having a CompactFlash card form factor and one or more flash memory devices carried by the housing. The portable memory module can also include a USB controller carried by the housing and coupled to the one or more flash memory devices. The portable memory module can further include a connector including a first portion coupled to the controller and a second portion configured to mate with a host device. In several embodiments, the connector includes a plurality of pins to transfer signals to and from the memory module. The pins are configured to mate with a fifty pin socket on the host device.

Abstract translation: 本文公开了便携式USB存储器模块或用于使用这种装置的装置和方法。 在一个实施例中，便携式存储器模块可以包括具有CompactFlash卡形状因子的壳体和由壳体承载的一个或多个闪存器件。 便携式存储器模块还可以包括由壳体承载并耦合到一个或多个闪存器件的USB控制器。 便携式存储器模块还可以包括连接器，该连接器包括耦合到控制器的第一部分和被配置为与主机设备配合的第二部分。 在几个实施例中，连接器包括多个引脚以将信号传送到存储器模块和从存储器模块传送信号。 引脚配置为与主机设备上的五十针插座配合。

公开(公告)号：US20080147899A1

公开(公告)日：2008-06-19

申请号：US11640527

申请日：2006-12-15

Applicant: Grady D. Lambert ,  Joydeep Chowdhury ,  Carson R. Stuart ,  Ryan C. McDaniel

Inventor： Grady D. Lambert ,  Joydeep Chowdhury ,  Carson R. Stuart ,  Ryan C. McDaniel

IPC: G06F3/00

CPC classification number: G11C7/1006 ,  G11C5/005 ,  G11C5/04

Abstract: Portable USB memory modules or devices and methods for using such devices are disclosed herein. In one embodiment, a portable memory module can include a housing having a CompactFlash card form factor and one or more flash memory devices carried by the housing. The portable memory module can also include a USB controller carried by the housing and coupled to the one or more flash memory devices. The portable memory module can further include a connector including a first portion coupled to the controller and a second portion configured to mate with a host device. In several embodiments, the connector includes a plurality of pins to transfer signals to and from the memory module. The pins are configured to mate with a fifty pin socket on the host device.

Abstract translation: 本文公开了便携式USB存储器模块或用于使用这种装置的装置和方法。 在一个实施例中，便携式存储器模块可以包括具有CompactFlash卡形状因子的壳体和由壳体承载的一个或多个闪存器件。 便携式存储器模块还可以包括由壳体承载并耦合到一个或多个闪存器件的USB控制器。 便携式存储器模块还可以包括连接器，该连接器包括耦合到控制器的第一部分和被配置为与主机设备配合的第二部分。 在几个实施例中，连接器包括多个引脚以将信号传送到存储器模块和从存储器模块传送信号。 引脚配置为与主机设备上的五十针插座配合。