公开(公告)号：US5838618A

公开(公告)日：1998-11-17

申请号：US927472

申请日：1997-09-11

申请人： Jian-Hsing Lee ,  Juang-Ker Yeh ,  Kuo-Reay Peng ,  Ming-Chou Ho

发明人： Jian-Hsing Lee ,  Juang-Ker Yeh ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C16/14

摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to remove charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a first relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a first moderately large positive voltage pulse to a first diffusion well. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float. The method to erase then proceeds with the source erasing to detrap the tunneling oxide of the flash EEPROM cell. The source erasing consists continued floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a second relatively large negative voltage pulse is applied to the control gate, as a second moderately large positive voltage pulse is applied to said source.

摘要翻译： 一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除闪存EEPROM单元的方法是从通道擦除开始，以从闪存EEPROM单元的浮动栅极去除电荷。 通道擦除包括将第一相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且同时向第一扩散阱施加第一适度大的正电压脉冲。 同时，对半导体衬底施加接地参考电位，同时使漏极和第二扩散阱浮动。 擦除的方法然后继续进行源擦除以去除快速EEPROM单元的隧穿氧化物。 源擦除继续浮置漏极和第二扩散阱，同时将接地参考电位施加到半导体衬底和第一扩散阱。 同时，向控制栅极施加第二相对较大的负电压脉冲，因为向所述源施加第二适度大的正电压脉冲。

公开(公告)号：US06303454B1

公开(公告)日：2001-10-16

申请号：US09590849

申请日：2000-06-09

申请人： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

发明人： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  G11C16/14 ,  H01L21/28273 ,  H01L29/7885

摘要： The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric layer 28, and a control gate 26. A drain 14 is formed adjacent to the gate structure by an masking 51 and ion implant process. Next, a source side doped region 18 is formed adjacent to and under a portion of the gate structure 22 24 28 26 by an masking and ion implant process. Spacers 32 are now formed on the sidewalls of the gate structure. A source 20 is formed overlapping portion of the side source doped region 18 and adjacent to the spacers 32. The side source doped region has a lower dopant concentration than the source 20. This method forms a snap-back memory cell wherein the side source doped region 18 is used to apply a high voltage to operate the EEPROM cell in a snap-back erase mode.

摘要翻译： 本发明提供了制造快速闪存EEPROMS设备的方法。 该方法开始于在衬底上形成栅极结构22 24 28 26。 栅极结构包括：隧道氧化物层22，浮置栅极24，整合电介质层28和控制栅极26.漏极14通过掩模51和离子注入工艺邻近栅极结构形成。 接下来，通过掩模和离子注入工艺在栅极结构22 24 28 26的一部分附近形成源极侧掺杂区18。 隔板32现在形成在栅极结构的侧壁上。 源极20形成在侧面源极掺杂区域18的重叠部分并且与间隔物32相邻。源极掺杂区域具有比源极20更低的掺杂剂浓度。该方法形成一个回写式存储器单元，其中侧面源掺杂 区域18用于施加高电压以快速擦除模式操作EEPROM单元。

公开(公告)号：US5949717A

公开(公告)日：1999-09-07

申请号：US928217

申请日：1997-09-12

申请人： Ming-Chou Ho ,  Juang-ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng

发明人： Ming-Chou Ho ,  Juang-ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/16

摘要： A method to erase data from a flash EEPROM cell while electrical charges trapped in the tunnel oxide of a flash EEPROM cell are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a first relatively high positive voltage pulse to the source of the flash EEPROM cell. Simultaneously a ground reference voltage is applied to the control gate and to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying a second relatively high positive voltage pulse to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate.

摘要翻译： 在快速EEPROM单元的隧道氧化物中捕获电荷的同时消除闪存EEPROM单元中的数据的方法，以在扩展的编程和擦除周期之后保持编程的阈值电压和擦除的阈值电压的适当分离。 擦除快闪EEPROM单元的方法首先是将第一相对较高的正电压脉冲施加到闪速EEPROM单元的源。 同时，对控制栅极和半导体衬底施加接地参考电压。 在同一时间，排水沟漂浮。 然后通过漂浮源极和漏极并将第二相对高的正电压脉冲施加到半导体衬底来去除快闪EEPROM单元。 同时，向控制栅极施加相当大的负电压脉冲。

公开(公告)号：US5862078A

公开(公告)日：1999-01-19

申请号：US907984

申请日：1997-08-11

申请人： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

发明人： Juang-Ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C16/349

摘要： A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to detrap the tunneling oxide of the flash EEPROM cell. The channel erasing consists floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a first relatively large negative voltage pulse is applied to the control gate, as a first moderately large positive voltage pulse is applied to said source. The method to erase then proceeds with the source erasing to remove charges from the floating gate of the flash EEPROM cell. The source erasing consists of applying a second relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a second moderately large positive voltage pulse to a first diffusion well. At the same time the ground reference potential continues to be applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float.

摘要翻译： 一种在闪存EEPROM的隧穿氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的方法是通过通道擦除来消除快速EEPROM单元的隧道氧化物。 通道擦除包括使漏极和第二扩散阱浮置，同时将接地参考电位施加到半导体衬底和第一扩散阱。 同时，第一相对较大的负电压脉冲施加到控制栅极，因为第一适度大的正电压脉冲被施加到所述源极。 擦除方法随后进行源擦除以从快闪EEPROM单元的浮动栅极去除电荷。 源擦除包括将第二相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且向第一扩散阱同时施加第二适度大的正电压脉冲。 同时，接地参考电位继续施加到半导体衬底，同时漏极和第二扩散阱被允许浮动。