公开(公告)号：US4356544A

公开(公告)日：1982-10-26

申请号：US268247

申请日：1981-05-29

申请人： Takuo Ono ,  Sigeo Fukui ,  Junichi Ookura

发明人： Takuo Ono ,  Sigeo Fukui ,  Junichi Ookura

IPC分类号： G06F1/02 ,  H02M1/084 ,  H02M7/48 ,  H02M7/5387 ,  H03B28/00 ,  H02M7/537

CPC分类号： H02M1/0845 ,  H02M7/53873

摘要： An apparatus for controlling an inverter main circuit has a memory circuit for storing digital control signals which correspond to 180.degree./n portions of output voltage waveforms of the inverter main circuit, where n is an integer. The memory circuit has a plurality of memory areas. One of the memory areas is designated by a digital signal supplied from a speed setting circuit. And the addresses of any memory area thus designated are designated by output signals of an up-down counter, one after another in ascending order of their serial numbers (forward direction) and in descending order of their serial numbers (backward direction). As they are designated, the memory regions corresponding to addresses supplies control signals. Every time the addressing direction is changed, the up-down counter generates a clock signal to a converter circuit which has 2n output terminals. In response to the clock signal supplied from the up-down counter, the converter circuit supplies signals to a waveform synthesizer circuit, one after another via the 2n output terminals. According to the signals from the converter circuit the waveform synthesizer circuit supplies to the inverter main circuit the control data in a predetermined order.

摘要翻译： 用于控制逆变器主电路的装置具有用于存储对应于逆变器主电路的输出电压波形的180°/ n部分的数字控制信号的存储电路，其中n是整数。 存储器电路具有多个存储区域。 其中一个存储区由一个由速度设定电路提供的数字信号指定。 并且由此指定的任何存储区域的地址由升序计数器的输出信号以序列号（向前方向）的升序和序列号（向后方向）的降序依次指定。 当它们被指定时，对应于地址的存储区域提供控制信号。 每次寻址方向改变时，升降计数器产生一个具有2n个输出端的转换器电路的时钟信号。 响应于从递增计数器提供的时钟信号，转换器电路经由2n个输出端子一个接一个地向波形合成器电路提供信号。 根据来自转换器电路的信号，波形合成器电路以预定顺序向控制数据提供控制数据。