公开(公告)号：US08768678B1

公开(公告)日：2014-07-01

申请号：US13245174

申请日：2011-09-26

Applicant: Valeria Mihalache ,  Christopher H. Kingsley ,  Jimmy Z. Wang ,  Kumar Deepak

Inventor： Valeria Mihalache ,  Christopher H. Kingsley ,  Jimmy Z. Wang ,  Kumar Deepak

IPC: G06F9/45 ,  G06F9/455 ,  G06F17/00

CPC classification number: G06F9/4881 ,  G06F17/5009

Abstract: One or more embodiments provide a load balancing solution for improving the runtime performance of parallel HDL simulators. During compilation each process is analyzed to determine a simulation cost based on complexity of the HDL processes. During simulation, processes to be executed in the same simulation cycle are scheduled using the simulation costs computed at compile-time in order to reduce the delay incurred during simulation.

Abstract translation: 一个或多个实施例提供用于改善并行HDL模拟器的运行时性能的负载平衡解决方案。 在编译期间，分析每个过程以基于HDL过程的复杂度来确定模拟成本。 在仿真期间，使用在编译时计算的仿真成本来调度在相同模拟周期中执行的过程，以减少模拟期间产生的延迟。

公开(公告)号：US08495539B1

公开(公告)日：2013-07-23

申请号：US13347301

申请日：2012-01-10

Applicant: Valeria Mihalache ,  Kumar Deepak ,  Hem C. Neema ,  Sonal Santan

Inventor： Valeria Mihalache ,  Kumar Deepak ,  Hem C. Neema ,  Sonal Santan

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method for compiling an HDL specification for simulation includes elaborating the HDL specification and determining singly-driven and multiply-driven nets of the elaborated circuit design. For each singly-driven net, a respective memory location is assigned to store a value of a corresponding driver of the net at runtime. For each multiply-driven net, a contiguous block of memory is assigned to store values of corresponding drivers of the net at runtime. For mixed language designs, this contiguous block contains values for drivers from all HDL languages involved. Simulation code that models the circuit design is generated. For each singly-driven net, the simulation code is configured to store a value of the corresponding driver of the singly-driven net in the respective memory location. For each multiply-driven net, the simulation code is configured to store the values of the corresponding drivers in the assigned block of memory. The generated simulation code is stored.

Abstract translation: 用于编译用于模拟的HDL规范的方法包括详细描述HDL规范并确定精心制作的电路设计的单驱动和多驱动网络。 对于每个单独驱动的网络，分配相应的存储器位置以在运行时存储网络的相应驱动器的值。 对于每个乘法驱动的网络，分配连续的内存块以在运行时存储网络的相应驱动程序的值。 对于混合语言设计，此连续块包含所有涉及的所有HDL语言的驱动程序的值。 生成模拟电路设计的仿真代码。 对于每个单驱动网络，模拟代码被配置为将单驱动网络的相应驱动器的值存储在相应的存储器位置中。 对于每个乘法驱动网络，模拟代码被配置为将相应驱动程序的值存储在指定的存储块中。 生成的模拟代码被存储。

公开(公告)号：US08265918B1

公开(公告)日：2012-09-11

申请号：US12579846

申请日：2009-10-15

Applicant: Hem C. Neema ,  Chi Bun Chan ,  Kumar Deepak ,  Nabeel Shirazi

Inventor： Hem C. Neema ,  Chi Bun Chan ,  Kumar Deepak ,  Nabeel Shirazi

IPC: G06F17/50

CPC classification number: G06F17/5027 ,  G06F17/5022

Abstract: Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.

Abstract translation: 协同仿真平台通常包括基于软件的系统和基于硬件的系统，其中电路设计的不同部分在基于软件的系统中模拟或在基于硬件的系统上仿真。 在电路设计模型可以共同模拟之前，电路设计必须被转换和配置成可以与特定的基于硬件的系统执行和接口的形式。 本发明的实施例提供了一种用于对电路设计的一部分进行协同仿真的方法，系统和制品，并且通过改进协同仿真配置和设置并提供协同仿真调整能力来实现本领域的进步 运行。

公开(公告)号：US07403961B1

公开(公告)日：2008-07-22

申请号：US10388935

申请日：2003-03-14

Applicant: Kumar Deepak ,  Sushama Ghanekar ,  Sonal Santan

Inventor： Kumar Deepak ,  Sushama Ghanekar ,  Sonal Santan

IPC: G06F12/00 ,  G06F17/30 ,  G06F17/50 ,  G06F11/00

CPC classification number: G06F12/0253 ,  G06F17/5022 ,  Y10S707/99957

Abstract: A method of dangling reference detection and garbage collection of VHDL objects within a program includes the steps of providing an Access Value having an Object Reference pointing to an Allocated Object and having and an Access Count pointer pointing to an integer object named Access Count which models a shared access count for the access values. The method sets the Object Reference and the Access Count pointer to null when constructing a new access value and enables an assignment of a negative Access Count to the shared access count when de-allocating a pointer to the Allocated Object. The method also maintains an exact count of a number of pointers pointing to the Allocated Object.

Abstract translation: 一种在程序中悬挂参考检测和VHDL对象的垃圾收集的方法，包括以下步骤：提供具有指向分配对象的对象引用的访问值，并具有指向指向访问计数的整数对象的访问计数指针，该整数对象对 访问值的共享访问计数。 当构造新的访问值时，该方法将“对象引用”和“访问计数”指针设置为“null”，并在将指针分配给“分配对象”时指定共享访问计数。 该方法还维护指向分配对象的指针数量的精确计数。

公开(公告)号：US07194705B1

公开(公告)日：2007-03-20

申请号：US10388692

申请日：2003-03-14

Applicant: Kumar Deepak ,  L. James Hwang ,  Singh Vinay Jitendra ,  Haibing Ma ,  Roger B. Milne ,  Nabeel Shirazi ,  Jeffrey D. Stroomer ,  Jimmy Zhenming Wang

Inventor： Kumar Deepak ,  L. James Hwang ,  Singh Vinay Jitendra ,  Haibing Ma ,  Roger B. Milne ,  Nabeel Shirazi ,  Jeffrey D. Stroomer ,  Jimmy Zhenming Wang

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.

Abstract translation: 描述了使用电路的一个或多个电路描述语言表示来模拟建模系统内的集成电路的方法，装置和计算机可读介质。 例如，电路的一个或多个电路描述语言表示的电路描述语言表示被转换成程序语言电路描述。 执行第一模拟处理并从其获得输入数据。 以输入数据作为参数输入来执行第二模拟处理以产生输出数据，第二模拟处理从程序语言电路描述导出。 通过第二次模拟处理产生的输出数据被提供给第一个仿真过程。

公开(公告)号：US07191412B1

公开(公告)日：2007-03-13

申请号：US11238432

申请日：2005-09-28

Applicant: Wei Lin ,  Sushama Ghanekar ,  Jimmy Zhenming Wang ,  Kumar Deepak

Inventor： Wei Lin ,  Sushama Ghanekar ,  Jimmy Zhenming Wang ,  Kumar Deepak

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: Method and apparatus for processing a circuit description including a hierarchy of components for logic simulation is described. Each component is described using one of a first hardware description language (HDL) and a second HDL. A root component and each component in the hierarchy below the root component described using an HDL identical to that of the root component is elaborated up to a cross-language boundary. The root component is described using one of the first HDL or the second HDL and each component at the cross-language boundary is described using the other of the first HDL or the second HDL. Each component at the cross-language boundary is stored in one of a first vector associated with the first HDL or a second vector associated with the second HDL based on language. A connection is established between each component at the cross-language boundary and a respective parent component.

Abstract translation: 描述用于处理包括用于逻辑模拟的组件的层次的电路描述的方法和装置。 使用第一硬件描述语言（HDL）和第二HDL之一描述每个组件。 使用与根组件相同的HDL描述的根组件下的层次结构中的根组件和每个组件被阐述为跨语言边界。 使用第一HDL或第二HDL中的一个描述根组件，并且使用第一HDL或第二HDL中的另一个来描述跨语言边界的每个组件。 跨语言边界的每个组件基于语言存储在与第一HDL相关联的第一向量中的一个或与第二HDL相关联的第二向量中。 在跨语言边界的每个组件和相应的父组件之间建立连接。

公开(公告)号：US08838431B1

公开(公告)日：2014-09-16

申请号：US13027683

申请日：2011-02-15

Applicant: Valeria Mihalache ,  Hem C. Neema ,  Kumar Deepak ,  Sonal Santan

Inventor： Valeria Mihalache ,  Hem C. Neema ,  Kumar Deepak ,  Sonal Santan

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: In one embodiment, a method is provided for generating dataflow-driven simulation code of a circuit design described with a combination of first and second HDLs. The circuit description is elaborated and a simulation dataflow graph of the circuit description is generated. Simulation code, configured to model execution of the design in a data-driven manner according to the simulation dataflow graph, is generated from the dataflow graph using a first HDL signal representation having a format compatible with the first HDL and a second HDL signal representation having a format compatible with the second HDL. For each instantiated module of the circuit description at a cross language boundary in the simulation dataflow graph, ports of the instantiated module are mapped to the first HDL signal representation and mapped to the second HDL signal representation.

Abstract translation: 在一个实施例中，提供了一种用于产生用第一和第二HDL的组合描述的电路设计的数据流驱动的模拟代码的方法。 详细描述电路描述，并生成电路描述的仿真数据流图。 模拟代码，被配置为根据模拟数据流图以数据驱动方式对设计的执行进行建模，使用具有与第一HDL兼容的格式的第一HDL信号表示和具有与第一HDL信号表示相关联的第二HDL信号表示从数据流图生成， 与第二HDL兼容的格式。 对于模拟数据流图中跨越语言边界的电路描述的每个实例化模块，实例化模块的端口映射到第一HDL信号表示并映射到第二HDL信号表示。

公开(公告)号：US08868396B1

公开(公告)日：2014-10-21

申请号：US12605077

申请日：2009-10-23

Applicant: Nabeel Shirazi ,  L. James Hwang ,  Chi Bun Chan ,  Hem C. Neema ,  Kumar Deepak

Inventor： Nabeel Shirazi ,  L. James Hwang ,  Chi Bun Chan ,  Hem C. Neema ,  Kumar Deepak

IPC: G06F17/50

CPC classification number: G06F17/5022

Abstract: A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.

Abstract translation: 本文公开了一种用于验证和调试高级编程系统的电路设计模块的方法和装置。 在高级编程环境中创建的电路设计必须经过多次转换，因为它被编译成可以在硬件中实现的形式。 在每个变换步骤中，必须用仿真模型验证电路的行为，并且如果转换改变了电路的行为，则进行调试。 所要求保护的发明提出了一种用于在不同仿真模型之间验证和调试的新方法，并通过利用高级电路设计的模块化结构来实现本领域的进步，以系统地识别不同仿真模型之间的模拟不匹配并确定电路的哪些部分 设计负责的差异。

公开(公告)号：US08516413B1

公开(公告)日：2013-08-20

申请号：US13468933

申请日：2012-05-10

Applicant: Sandeep S. Deshpande ,  Hem C. Neema ,  Valeria Mihalache ,  Kumar Deepak ,  Sonal Santan ,  David K. Liddell

Inventor： Sandeep S. Deshpande ,  Hem C. Neema ,  Valeria Mihalache ,  Kumar Deepak ,  Sonal Santan ,  David K. Liddell

IPC: G06F9/45

CPC classification number: G06F17/5045 ,  G06F17/5022

Abstract: One or more embodiments provide a method of HDL simulation that determines dependencies, forcing characteristics, and strength characteristics of nets for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

Abstract translation: 一个或多个实施例提供了一种HDL模拟方法，其确定编译期间整个电路设计的网络的依赖性，强制特性和强度特性。 基于相应网的确定的特性，分别为每个网络生成模拟代码和数据结构。 结果，不是为了实现能够处理每个可能的特征组合的每个网络的模拟实现代码，而是可以生成用于模拟网络的较不复杂的代码和数据结构。

公开(公告)号：US08418095B1

公开(公告)日：2013-04-09

申请号：US13468927

申请日：2012-05-10

Applicant: Hem C. Neema ,  Sonal Santan ,  Kumar Deepak

Inventor： Hem C. Neema ,  Sonal Santan ,  Kumar Deepak

IPC: G06F17/50

CPC classification number: G06F17/5027

Abstract: One or more embodiments provide a method of HDL simulation that determines characteristics of nets, such as shorting of nets, non-blocking assignments, etc., for the entire circuit design during compilation. Simulation code and data structures are generated for each net, individually, based on the determined characteristics of the respective net. As a result, rather than implementing code for simulation of each net capable of handling every possible combination of the characteristics, less complex code and data structures may be generated for simulation of the nets.

Abstract translation: 一个或多个实施例提供了HDL模拟的方法，其确定网络的特性，例如在编译期间整个电路设计的网络的短路，非阻塞分配等。 基于相应网的确定的特性，分别为每个网络生成模拟代码和数据结构。 结果，不是为了实现能够处理每个可能的特征组合的每个网络的模拟实现代码，而是可以生成用于模拟网络的较不复杂的代码和数据结构。