Method for reducing stray conductive material near vertical surfaces in
semiconductor manufacturing processes
    1.
    发明授权
    Method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes 失效
    在半导体制造工艺中减少垂直表面附近杂散导电材料的方法

    公开(公告)号:US5888894A

    公开(公告)日:1999-03-30

    申请号:US965912

    申请日:1997-11-07

    CPC分类号: H01L21/76895

    摘要: A method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes comprising the following steps. Deposit the gate oxide, polysilicon and cap oxide layers. Apply a Poly1A mask. The Poly1A mask pattern comprises the Poly1 areas that are part of the final circuit layout as well as additional Poly1 areas that are included to provide planar surfaces to prevent stringer formation. Etch the cap, polysilicon and gate oxide layers to partially form the transistor gate structures. Form oxide spacers on the sides of the transistor gate structures. Apply a source/drain mask. Deposit source/drain dopants to form diffusions. Deposit an interlayer dielectric. Mask and pattern contacts to the diffusions and the Poly1 layer. Deposit blanket TiN/Ti layer(s). Pattern the TiN/Ti layer(s) using a TiN/Ti mask and a dry anisotropic etch. Patterning the TiN/Ti layer(s) may create TiN/Ti stringers along vertical surfaces of the interconnect layer. However, by defining the Poly1A mask pattern to leave Poly1 in pre-defined potential stringer problem areas, these surfaces remain planar and thus free of stringers. Next, apply a Poly1B mask. The Polyl1B mask is defined such that the final Poly1 pattern is the logical AND of the Poly1A mask pattern and the inverse of the Poly1B mask. Then etch the cap, polysilicon and gate oxide layers to complete formation of the transistor gate structures.

    摘要翻译: 一种用于在半导体制造工艺中减少垂直表面附近的杂散导电材料的方法,包括以下步骤。 沉积栅极氧化物,多晶硅和氧化铟层。 应用Poly1A面膜。 Poly1A掩模图案包括作为最终电路布局的一部分的Poly1区域以及额外的Poly1区域,其被包括以提供平面表面以防止纵梁形成。 蚀刻帽,多晶硅和栅极氧化物层以部分地形成晶体管栅极结构。 在晶体管栅极结构的侧面上形成氧化物间隔物。 应用源/漏屏蔽。 沉积源/漏掺杂物形成扩散。 沉积层间电介质 掩模和图案与扩散和Poly1层接触。 沉积层TiN / Ti层。 使用TiN / Ti掩模和干法各向异性蚀刻对TiN / Ti层进行成型。 对TiN / Ti层进行图案化可以在互连层的垂直表面上产生TiN / Ti桁条。 然而,通过定义Poly1A掩模图案使Poly1保留在预定义的潜在纵向问题区域中,这些表面保持平面,因此没有桁条。 接下来,应用Poly1B掩模。 定义Polyl1B掩模,使得最终的Poly1图案是Poly1A掩模图案与Poly1B掩模的倒数的逻辑AND。 然后蚀刻帽,多晶硅和栅极氧化物层以完成晶体管栅极结构的形成。