公开(公告)号：US07881094B2

公开(公告)日：2011-02-01

申请号：US12269598

申请日：2008-11-12

申请人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  KangYong Kim ,  Henry F. Huang

发明人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  KangYong Kim ,  Henry F. Huang

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C5/147 ,  G11C7/14 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0038

摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage for a resistive sense memory (RSM) cell, such as an STRAM cell. A dummy reference cell used to generate a reference voltage to sense a resistive state of an adjacent RSM cell. The dummy reference cell comprises a switching device, a resistive sense element (RSE) programmed to a selected resistive state, and a dummy resistor coupled to the RSE. A magnitude of the reference voltage is set in relation to the selected resistive state of the RSE and the resistance of the dummy resistor.

摘要翻译： 本发明的各种实施例一般涉及一种用于为诸如STRAM单元的电阻式感测存储器（RSM）单元产生参考电压的装置和相关联的方法。 用于产生参考电压以感测相邻RSM单元的电阻状态的虚拟参考单元。 虚拟参考单元包括开关装置，被编程为选择的电阻状态的电阻感测元件（RSE）和耦合到RSE的虚拟电阻。 参考电压的大小相对于RSE的选定电阻状态和虚拟电阻器的电阻设定。

公开(公告)号：US20100118588A1

公开(公告)日：2010-05-13

申请号：US12269598

申请日：2008-11-12

申请人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  KangYong Kim ,  Henry F. Huang

发明人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  KangYong Kim ,  Henry F. Huang

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C11/14

CPC分类号： G11C13/004 ,  G11C5/147 ,  G11C7/14 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0038

摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage for a resistive sense memory (RSM) cell, such as an STRAM cell. A dummy reference cell used to generate a reference voltage to sense a resistive state of an adjacent RSM cell. The dummy reference cell comprises a switching device, a resistive sense element (RSE) programmed to a selected resistive state, and a dummy resistor coupled to the RSE. A magnitude of the reference voltage is set in relation to the selected resistive state of the RSE and the resistance of the dummy resistor.

摘要翻译： 本发明的各种实施例一般涉及一种用于为诸如STRAM单元的电阻式感测存储器（RSM）单元产生参考电压的装置和相关联的方法。 用于产生参考电压以感测相邻RSM单元的电阻状态的虚拟参考单元。 虚拟参考单元包括开关装置，被编程为选择的电阻状态的电阻感测元件（RSE）和耦合到RSE的虚拟电阻。 参考电压的大小相对于RSE的选定电阻状态和虚拟电阻器的电阻设定。

公开(公告)号：US07936625B2

公开(公告)日：2011-05-03

申请号：US12409671

申请日：2009-03-24

申请人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  KangYong Kim ,  Henry F. Huang

发明人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  KangYong Kim ,  Henry F. Huang

IPC分类号： G11C7/00

CPC分类号： G11C7/1039 ,  G11C7/08 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/56 ,  G11C11/5607 ,  G11C13/00 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054

摘要： Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the first memory cell while a second read voltage from a second memory cell is stored in a second VSE. In other embodiments, bias currents are simultaneously applied to a first set of memory cells from the array while read voltages generated thereby are stored in a corresponding first set of VSEs. The read voltages are sequentially compared with at least one reference value to serially output a logical sequence corresponding to the memory states of the first set of memory cells while read voltages are stored for a second set of memory cells in a second set of VSEs.

摘要翻译： 各种实施例通常涉及用于执行流水线检测操作的方法和装置。 在一些实施例中，来自第一存储器单元的读取电压被存储在电压存储元件（VSE）中并与参考电压进行比较，以识别第一存储器单元的相应存储器状态，而来自第二存储器单元的第二读取电压为 存储在第二个VSE中。 在其他实施例中，偏置电流同时从阵列施加到第一组存储器单元，而由此产生的读取电压被存储在对应的第一组VSE中。 读取电压与至少一个参考值顺序地比较，以串行输出对应于第一组存储器单元的存储器状态的逻辑序列，而在第二组VSE中为第二组存储器单元存储读取电压。

公开(公告)号：US20100246250A1

公开(公告)日：2010-09-30

申请号：US12409671

申请日：2009-03-24

申请人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  KangYong Kim ,  Henry F. Huang

发明人： Yiran Chen ,  Hai Li ,  Harry Hongyue Liu ,  KangYong Kim ,  Henry F. Huang

IPC分类号： G11C11/14 ,  G11C7/00

CPC分类号： G11C7/1039 ,  G11C7/08 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/56 ,  G11C11/5607 ,  G11C13/00 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0054

摘要： Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the first memory cell while a second read voltage from a second memory cell is stored in a second VSE. In other embodiments, bias currents are simultaneously applied to a first set of memory cells from the array while read voltages generated thereby are stored in a corresponding first set of VSEs. The read voltages are sequentially compared with at least one reference value to serially output a logical sequence corresponding to the memory states of the first set of memory cells while read voltages are stored for a second set of memory cells in a second set of VSEs.

摘要翻译： 各种实施例通常涉及用于执行流水线检测操作的方法和装置。 在一些实施例中，来自第一存储器单元的读取电压被存储在电压存储元件（VSE）中并与参考电压进行比较，以识别第一存储器单元的相应存储器状态，而来自第二存储器单元的第二读取电压为 存储在第二个VSE中。 在其他实施例中，偏置电流同时从阵列施加到第一组存储器单元，而由此产生的读取电压被存储在对应的第一组VSE中。 读取电压与至少一个参考值顺序地比较，以串行输出对应于第一组存储器单元的存储器状态的逻辑序列，而在第二组VSE中为第二组存储器单元存储读取电压。