公开(公告)号：US4949162A

公开(公告)日：1990-08-14

申请号：US201928

申请日：1988-06-03

申请人： Yoichi Tamaki ,  Kiyoji Ikeda ,  Toru Nakamura ,  Akihisa Uchida ,  Toru Koizumi ,  Hiromichi Enami ,  Satoru Isomura ,  Shinji Nakajima ,  Katsumi Ogiue ,  Kaoru Ohgaya

发明人： Yoichi Tamaki ,  Kiyoji Ikeda ,  Toru Nakamura ,  Akihisa Uchida ,  Toru Koizumi ,  Hiromichi Enami ,  Satoru Isomura ,  Shinji Nakajima ,  Katsumi Ogiue ,  Kaoru Ohgaya

IPC分类号： H01L23/485 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L24/02 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/05042 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/3025

摘要： A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).

摘要翻译： 一种多层半导体集成电路，其具有多个布线层，其中至少在布置在栅格中的布线沟道区上的下层的布线延伸。 虚拟基座由与形成下层的线相同的导电层形成，并且布置在布线沟道区域的相交区域中，其中没有放置下层的线。 一种制造这样的半导体集成电路的方法包括以下步骤：制备用于在布线沟道区域的所有交叉区域中布置虚设基座的虚拟基座布局数据和用于在预定布线通道上形成下层的线的线路布局数据 布线通道区域，并且通过逻辑和（OR）组合虚拟基座布局数据和线路布局数据。