公开(公告)号：US5371713A

公开(公告)日：1994-12-06

申请号：US207677

申请日：1994-03-09

Applicant: Katsumi Ogiue ,  Yukio Suzuki ,  Ikuro Masuda ,  Masanori Odaka ,  Hideaki Uchida

Inventor： Katsumi Ogiue ,  Yukio Suzuki ,  Ikuro Masuda ,  Masanori Odaka ,  Hideaki Uchida

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/34 ,  G11C11/414 ,  G11C11/417 ,  H03K19/0944

CPC classification number: G11C7/1057 ,  G11C7/00 ,  G11C7/062 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  H03K19/09448

Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

公开(公告)号：US5367490A

公开(公告)日：1994-11-22

申请号：US967133

申请日：1992-10-27

Applicant: Kazuhiro Akimoto ,  Masami Usami ,  Katsumi Ogiue ,  Hiroshi Murayama ,  Hitoshi Abe ,  Masamori Kashiyama ,  Yoshikuni Kobayashi ,  Satoru Isomura ,  Kinya Mitsumoto

Inventor： Kazuhiro Akimoto ,  Masami Usami ,  Katsumi Ogiue ,  Hiroshi Murayama ,  Hitoshi Abe ,  Masamori Kashiyama ,  Yoshikuni Kobayashi ,  Satoru Isomura ,  Kinya Mitsumoto

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/22 ,  H03K5/24 ,  G11C7/00

CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C7/10 ,  H03K5/2418

Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Abstract translation: 公开了一种半导体集成电路，其中用于与RAMS交换信号的逻辑电路，其中RAMS被布置在半导体芯片或基板上的中心处，根据信号的种类被分成多个逻辑电路，并且分开的逻辑电路是 以使得与RAM的信号传输路径的距离最小化的方式设置在RAM周围，并且为了实现对RAMS的高速访问。

公开(公告)号：US5354699A

公开(公告)日：1994-10-11

申请号：US964824

申请日：1992-10-22

Applicant: Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

Inventor： Takahide Ikeda ,  Kouichirou Yamada ,  Osamu Saito ,  Masanori Odaka ,  Nobuo Tamba ,  Katsumi Ogiue ,  Atsushi Hiraishi ,  Atsuo Watanabe ,  Mitsuru Hirao ,  Akira Fukami ,  Masayuki Ohayashi ,  Tadashi Kuramoto

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/8249 ,  H01L27/06 ,  H01L21/265

CPC classification number: H01L21/28026 ,  H01L21/28525 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/009

Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Abstract translation: 公开了通过简化的工艺制造的双极CMOS LSI，并实现更高的集成密度以及更高的工作速度，其中双极晶体管的基极引出电极和p沟道MISFET的各自的栅电极和 CMOS晶体管的n沟道MISFET由相同的导体膜制成，并且p沟道MISFET的栅电极的导体膜为p型，而n沟道MISFET的栅电极的导体膜为 n型。

公开(公告)号：US5214302A

公开(公告)日：1993-05-25

申请号：US807411

申请日：1991-12-13

Applicant: Akihisa Uchida ,  Keiichi Higeta ,  Nobuo Tamba ,  Masanori Odaka ,  Katsumi Ogiue

Inventor： Akihisa Uchida ,  Keiichi Higeta ,  Nobuo Tamba ,  Masanori Odaka ,  Katsumi Ogiue

IPC: H01L27/06 ,  H01L27/11 ,  H01L29/732

CPC classification number: H01L29/7325 ,  H01L27/0623 ,  H01L27/1112

Abstract: A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region. The bipolar transistor is characterized as a self-alignment transistor and that the insulating side wall spacers corresponding to the gate and base (emitter) electrodes are formed by a same lever.

Abstract translation: 一种半导体集成电路器件，具有以下结构，其中以下各个区域，即用于形成每个双极晶体管的基极和发射极区域的第一区域，用于形成双极性的集电极导出区域的第二区域 晶体管和用于形成每个MISFET的第三区域从半导体衬底的主表面突出，由此可以实现MISFET之间以及这些MISFET与具有相同隔离结构的双极晶体管之间的隔离，并且在 与双极晶体管之间的隔离相同的制造步骤。 此外，在该器件中，双极晶体管的基极区域电自自对准地连接到形成在主表面上以围绕发射极区域的基极。 双极晶体管的特征在于自对准晶体管，并且与栅极和基极（发射极）电极对应的绝缘侧壁间隔物由相同的杆形成。

公开(公告)号：US4260430A

公开(公告)日：1981-04-07

申请号：US50202

申请日：1979-06-20

Applicant: Kazuo Itoh ,  Katsumi Ogiue ,  Akio Hayasaka

Inventor： Kazuo Itoh ,  Katsumi Ogiue ,  Akio Hayasaka

IPC: H01L21/8222 ,  H01L21/33 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/06 ,  H01L27/082 ,  H01L29/70 ,  H01L29/73 ,  H03K19/091 ,  H01L21/263 ,  H01L7/36

CPC classification number: H01L21/8226 ,  H01L27/0237

Abstract: An I.sup.2 L device is disclosed wherein the P type injector region of a PNP transistor is formed so as to be buried in an N.sup.- type epitaxial layer below the P type collector region of the PNP transistor, whereby the carrier injection efficiency of the transistor is improved and a high switching speed is obtained. The I.sup.2 L device further includes an inversed NPN transistor wherein the abovementioned P type collector region of the PNP transistor works as a base region of the NPN transistor, an N type collector region is formed in the P type base region, and the abovementioned P type injector region extends between the N.sup.- type epitaxial layer and an N.sup.+ type substrate except below the N type collector region so that the effective emitter portion of the NPN transistor is limited to a specific area immediately below the N type collector region, thereby to reduce the power consumption.

Abstract translation: 公开了一种I2L器件，其中PNP晶体管的P型注入器区域被形成为埋入在PNP晶体管的P型集电极区域之下的N型外延层中，从而提高了晶体管的载流子注入效率 并获得高切换速度。 I2L器件还包括反向NPN晶体管，其中PNP晶体管的上述P型集电极区域用作NPN晶体管的基极区域，在P型基极区域中形成N型集电极区域，并且上述P型注入器 区域在N型外延层和除了N型集电极区域之外的N +型衬底之间延伸，使得NPN晶体管的有效发射极部分被限制在紧邻N型集电极区域的特定区域，从而降低功率 消费。

公开(公告)号：US5243208A

公开(公告)日：1993-09-07

申请号：US853090

申请日：1992-03-17

Applicant: Satoru Isomura ,  Masato Iwabuchi ,  Katsumi Ogiue

Inventor： Satoru Isomura ,  Masato Iwabuchi ,  Katsumi Ogiue

IPC: H01L21/60 ,  H01L23/057 ,  H01L25/065 ,  H01L25/18 ,  H01L27/118

CPC classification number: H01L24/05 ,  H01L23/057 ,  H01L24/03 ,  H01L24/11 ,  H01L25/0652 ,  H01L25/18 ,  H01L27/118 ,  H01L27/11898 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/11474 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48699 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S257/903

Abstract: In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layer which extend parallel with each other are set so that noises are canceled in differential sense circuits.

Abstract translation: 在具有RAM的门阵列中，配置逻辑部分和门阵列的I / O单元电路的旁路信号线被布置成在RAM上方延伸。 为了最小化相互干扰，从与旁路信号线相邻的层形成的信号线被设置成与直角信号线相交。 此外，设置彼此平行延伸的不同层中的互连间距，使得差分感测电路中的噪声被消除。

公开(公告)号：US5177584A

公开(公告)日：1993-01-05

申请号：US647220

申请日：1991-01-28

Applicant: Akihisa Uchida ,  Yuji Yatsuda ,  Katsumi Ogiue ,  Kazuo Nakazato ,  Takahiro Onai

Inventor： Akihisa Uchida ,  Yuji Yatsuda ,  Katsumi Ogiue ,  Kazuo Nakazato ,  Takahiro Onai

IPC: H01L27/082

CPC classification number: H01L27/0828

Abstract: A bipolar SRAM which includes a forward bipolar transistor and a reverse bipolar transistor on an identical semiconductor substrate, is disclosed. Concretely, the base region of the reverse bipolar transistor is formed at a deeper position of the substrate than the base region of the forward bipolar transistor, thereby to heighten the cutoff frequency f.sub.T of the reverse bipolar transistor.

Abstract translation: 公开了一种在同一半导体衬底上包括前向双极晶体管和反向双极晶体管的双极性SRAM。 具体地说，反向双极型晶体管的基极区域形成在基板的比前方双极型晶体管的基极区域更深的位置，从而提高反向双极型晶体管的截止频率fT。

公开(公告)号：US5103282A

公开(公告)日：1992-04-07

申请号：US579698

申请日：1990-09-10

Applicant: Satoru Isomura ,  Masato Iwabuchi ,  Katsumi Ogiue

Inventor： Satoru Isomura ,  Masato Iwabuchi ,  Katsumi Ogiue

IPC: H01L21/60 ,  H01L21/82 ,  H01L21/822 ,  H01L23/057 ,  H01L25/065 ,  H01L25/18 ,  H01L27/04 ,  H01L27/118

CPC classification number: H01L24/05 ,  H01L23/057 ,  H01L24/03 ,  H01L24/11 ,  H01L25/0652 ,  H01L25/18 ,  H01L27/118 ,  H01L27/11898 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05138 ,  H01L2224/11474 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S257/903

Abstract: In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.

公开(公告)号：US4907063A

公开(公告)日：1990-03-06

申请号：US51699

申请日：1987-05-20

Applicant: Daisuke Okada ,  Akihisa Uchida ,  Toshihiko Takakura ,  Shinji Nakashima ,  Nobuhiko Ohno ,  Katsumi Ogiue

Inventor： Daisuke Okada ,  Akihisa Uchida ,  Toshihiko Takakura ,  Shinji Nakashima ,  Nobuhiko Ohno ,  Katsumi Ogiue

IPC: H01L21/31 ,  H01L21/331 ,  H01L21/76 ,  H01L21/763 ,  H01L29/73 ,  H01L29/732

CPC classification number: H01L21/763 ,  H01L21/76 ,  Y10S438/978

Abstract: A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

公开(公告)号：US4858189A

公开(公告)日：1989-08-15

申请号：US121914

申请日：1987-11-17

Applicant: Katsumi Ogiue ,  Yukio Suzuki ,  Ikuro Masuda ,  Masanori Odaka ,  Hideaki Uchida

Inventor： Katsumi Ogiue ,  Yukio Suzuki ,  Ikuro Masuda ,  Masanori Odaka ,  Hideaki Uchida

IPC: G11C11/413 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C11/34 ,  G11C11/414 ,  G11C11/417 ,  H03K19/0944

CPC classification number: G11C7/1057 ,  G11C7/00 ,  G11C7/062 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1096 ,  G11C7/12 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  H03K19/09448

Abstract: In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

Abstract translation: 为了提供高速度和低功耗，构造半导体集成电路以利用CMOS元件和双极晶体管。 双极晶体管用于输出部分以利用其运行速度，以允许输出线的快速充电和放电。 同时，电路的主要工作部分使用低功耗的CMOS元件。 这种布置在存储器电路中是特别有利的。