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Patent Agency Ranking
公开(公告)号：US20110161910A1
公开(公告)日：2011-06-30
申请号：US12975988
申请日：2010-12-22
Applicant: Katsuya OGATA , Hiroyuki Rokugawa
Inventor： Katsuya OGATA , Hiroyuki Rokugawa
IPC: G06F17/50
CPC classification number: G06F17/5036
Abstract: A design support apparatus includes: a circuit-data generation unit to generate circuit data based on layout information of a semiconductor integrated circuit; and a parameter determination unit to set a first parameter relating to mechanical stress exerted on a transistor including at least one of a plurality of gates in a diffusion region, wherein the circuit-data generation unit obtains a mobility of the transistor based on the first parameter and reflects the mobility in the circuit data.
Abstract translation: 设计支持装置包括：电路数据生成单元，用于基于半导体集成电路的布局信息生成电路数据; 以及参数确定单元，用于设置与包括扩散区域中的多个栅极中的至少一个的晶体管相关的机械应力的第一参数，其中所述电路数据生成单元基于所述第一参数获得所述晶体管的迁移率 并反映电路数据中的移动性。
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公开(公告)号：US20120329266A1
公开(公告)日：2012-12-27
申请号：US13494145
申请日：2012-06-12
Applicant: Takanori Hiramoto , Toshio Hino , Tsuyoshi Sakata , Yutaka Mizuno , Katsuya Ogata
Inventor： Takanori Hiramoto , Toshio Hino , Tsuyoshi Sakata , Yutaka Mizuno , Katsuya Ogata
IPC: G06F17/50 , H01L21/768
CPC classification number: H01L27/0207 , H01L27/11807
Abstract: A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.
Abstract translation: 交替地设置并列布置的多个栅极电极图案，以作为在双重图案化的第一曝光步骤中形成的第一图案和作为在第二曝光步骤中形成的第二图案。 随后，布置包括通过将第一图案和第二图案中的一个平行地连接而形成的晶体管对的电路。 这降低了由双重图案化引起的晶体管特性变化的风险。
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公开(公告)号：US4802840A
公开(公告)日：1989-02-07
申请号：US138843
申请日：1987-11-25
Applicant: Morio Fukuda , Masayuki Hanada , Hideo Inutsuka , Katsuya Ogata
Inventor： Morio Fukuda , Masayuki Hanada , Hideo Inutsuka , Katsuya Ogata
CPC classification number: B29C47/0028 , B28B3/269 , B29C47/12 , B29L2031/60 , Y10T428/24149
Abstract: An extrusion die for forming a honeycomb stucture has a lattice molding groove formed in the outlet surface of the die body. In the inlet surface of the die body there are formed plural independent supply passages that are opposite to the intersecting portions of the molding groove and extend toward the outlet surface. A through hole is designed to communicate adjacent supply passages at a place that forms part of the partition wall between the supply passages and contacts with the molding groove. This through hole takes the combined shape of a trapezoid with the width of the molding groove as its top side and with the diameter of the supply passage as its maximum base side and a semicircle having said base side as its diameter.
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公开(公告)号：US09021405B2
公开(公告)日：2015-04-28
申请号：US13494145
申请日：2012-06-12
Applicant: Takanori Hiramoto , Toshio Hino , Tsuyoshi Sakata , Yutaka Mizuno , Katsuya Ogata
Inventor： Takanori Hiramoto , Toshio Hino , Tsuyoshi Sakata , Yutaka Mizuno , Katsuya Ogata
IPC: G06F17/50 , H01L27/02 , H01L27/118
CPC classification number: H01L27/0207 , H01L27/11807
Abstract: A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.
Abstract translation: 交替地设置并列布置的多个栅极电极图案，以作为在双重图案化的第一曝光步骤中形成的第一图案和作为在第二曝光步骤中形成的第二图案。 随后，布置包括通过将第一图案和第二图案中的一个平行地连接而形成的晶体管对的电路。 这降低了由双重图案化引起的晶体管特性变化的风险。
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公开(公告)号：US08386991B2
公开(公告)日：2013-02-26
申请号：US12975988
申请日：2010-12-22
Applicant: Katsuya Ogata , Hiroyuki Rokugawa
Inventor： Katsuya Ogata , Hiroyuki Rokugawa
IPC: G06F17/50
CPC classification number: G06F17/5036
Abstract: A design support apparatus includes: a circuit-data generation unit to generate circuit data based on layout information of a semiconductor integrated circuit; and a parameter determination unit to set a first parameter relating to mechanical stress exerted on a transistor including at least one of a plurality of gates in a diffusion region, wherein the circuit-data generation unit obtains a mobility of the transistor based on the first parameter and reflects the mobility in the circuit data.
Abstract translation: 设计支持装置包括：电路数据生成单元，用于基于半导体集成电路的布局信息生成电路数据; 以及参数确定单元，用于设置与包括扩散区域中的多个栅极中的至少一个的晶体管相关的机械应力的第一参数，其中所述电路数据生成单元基于所述第一参数获得所述晶体管的迁移率 并反映电路数据中的移动性。
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