摘要:
A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31). That is, the D/A converter circuit (21) provides a voltage signal (VRH) to the capacitors (25, 27), in response to a value (D=2) of a digital signal (B0, B1), provides voltage signals (VRH, VRL) to the capacitors (25, 27), respectively, in response to a value (D=1) of the signal (B0, B1), and provides the voltage signal (VRL) to the capacitors (25, 27), in response to a value (D=0) of the signal (B0, B1).
摘要:
A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31). That is, the D/A converter circuit (21) provides a voltage signal (VRH) to the capacitors (25, 27), in response to a value (D=2) of a digital signal (B0, B1), provides voltage signals (VRH, VRL) to the capacitors (25, 27), respectively, in response to a value (D=1) of the signal (B0, B1), and provides the voltage signal (VRL) to the capacitors (25, 27), in response to a value (D=0) of the signal (B0, B1).