公开(公告)号：US09307171B2

公开(公告)日：2016-04-05

申请号：US14234878

申请日：2012-07-25

申请人： Shoji Kawahito ,  Isamu Takai

发明人： Shoji Kawahito ,  Isamu Takai

IPC分类号： H04N5/374 ,  H04N5/3745 ,  H04N5/359 ,  H01L31/11 ,  H01L27/146

CPC分类号： H04N5/3742 ,  H01L27/14612 ,  H01L31/11 ,  H04N5/3594 ,  H04N5/3745 ,  H04N5/37452

摘要： A pixel 10 includes a photodiode PD which is provided between a first barrier region 21 forming a first potential barrier B1 and a second barrier region 27 forming a second potential barrier B2, a first floating diffusion region F1 which is provided adjacent to the first barrier region 21, and to which a first electric charge generated in the photodiode PD is transferred, and a second floating diffusion region F2 which is provided adjacent to the second barrier region 27, and into which a second electric charge generated in the photoelectric conversion region PD flows, and in which a part of the flowing-in second electric charge is accumulated. The second potential barrier B2 is lower than the first potential barrier B1.

摘要翻译： 像素10包括设置在形成第一势垒B1的第一势垒区域21和形成第二势垒B2的第二势垒区域27之间的光电二极管PD，与第一势垒区域相邻设置的第一浮动扩散区域F1 21，并且传输在光电二极管PD中产生的第一电荷的第二浮动扩散区域F2和与第二势垒区域27相邻设置并且在光电转换区域PD中产生的第二电荷流过的第二浮动扩散区域F2 并且其中积聚了一部分流入的第二电荷。 第二势垒B2低于第一势垒B1。

公开(公告)号：US09236879B2

公开(公告)日：2016-01-12

申请号：US13985723

申请日：2012-02-17

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H03M1/12 ,  H03M1/18 ,  H04N5/378 ,  H03M1/16 ,  H03M1/40 ,  H03M1/56

CPC分类号： H03M1/18 ,  H03M1/162 ,  H03M1/403 ,  H03M1/56 ,  H03M3/39 ,  H03M3/46 ,  H04N5/378

摘要： According to this A/D converter, a first A/D conversion operation for performing integral A/D conversion and a second A/D conversion operation for performing cyclic A/D conversion are realized based on control of operational procedures in a same circuit configuration. Moreover, in the first A/D conversion operation, since a capacity of a capacitor used in the integration of an output signal is greater than a capacity of a capacitor used for storing an input analog signal and a standard reference voltage, the analog signal that is input in the integral A/D conversion is attenuated according to the capacity ratio and subject to sampling and integration. Consequently, the voltage range of the analog signal that is output in the integral A/D conversion also decreases according to the capacity ratio of the capacitors, and the A/D converter can be therefore constructed with a single-ended configuration.

摘要翻译： 根据该A / D转换器，通过在相同的电路配置中的操作程序的控制来实现用于执行积分A / D转换和用于执行循环A / D转换的第二A / D转换操作的第一A / D转换操作 。 此外，在第一A / D转换操作中，由于在输出信号的积分中使用的电容器的容量大于用于存储输入模拟信号和标准参考电压的电容器的容量，所以模拟信号 在积分A / D转换中输入根据容量比衰减并进行采样和积分。 因此，根据电容器的容量比，在积分A / D转换中输出的模拟信号的电压范围也降低，因此可以以单端配置构建A / D转换器。

公开(公告)号：US08692701B2

公开(公告)日：2014-04-08

申请号：US13599195

申请日：2012-08-30

申请人： Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

发明人： Shoji Kawahito ,  Sung Wook Jung ,  Osamu Kobayashi ,  Yasuhide Shimizu ,  Takahiro Miki ,  Takashi Morie ,  Hirotomo Ishii

IPC分类号： H03M1/38

CPC分类号： H03M1/06 ,  H03M1/167

摘要： A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

摘要翻译： 流水线A / D转换器电路包括：采样保持电路，被配置为采样和保持模拟输入信号，并输出采样保持信号;以及A / D转换器电路，包括级联地彼此连接的A / D转换器电路部分， 并以流水线形式执行A / D转换。 每级的流水线A / D转换器电路部分包括子A / D转换器电路，乘法器D / A转换器电路和预充电电路。 子A / D转换电路包括比较器，A / D将输入信号转换为预定位的数字信号; D / A转换器电路，用于对来自子A / D转换器的数字信号进行D / A转换 电路作为参考电压产生的模拟控制信号作为参考值，通过基于模拟控制信号的采样电容进行采样，保持和放大输入信号。

公开(公告)号：US08587709B2

公开(公告)日：2013-11-19

申请号：US13056816

申请日：2009-07-31

申请人： Shoji Kawahito ,  Hiroaki Takeshita

发明人： Shoji Kawahito ,  Hiroaki Takeshita

IPC分类号： H04N3/14 ,  H04N5/335 ,  C12Q1/68 ,  H01J40/00

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14641

摘要： The present invention provides a high-speed charge-transfer photodiode encompassing a first conductivity type semiconductor layer (20) serving as a charge-generation region; and a second conductivity type surface-buried region (21a) serving as a charge-transfer region of charges generated by the charge-generation region, wherein a specified direction in the surface-buried region (21a) provided along a plane parallel to a surface of the semiconductor layer (20) is assigned as a charge-transfer direction of the charges, and at least one of a variation of widths of the surface-buried region (21a) measured in an orthogonal direction to the charge-transfer direction and a variation of impurity concentration distributions of the surface-buried region (21a), which are measured along the charge-transfer direction, is determined such that an electric field distribution in the charge-transfer direction is constant.

摘要翻译： 本发明提供一种包含用作电荷产生区域的第一导电类型半导体层（20）的高速电荷转移光电二极管; 以及作为由电荷产生区域产生的电荷的电荷转移区域的第二导电型表面埋藏区域，其中沿着平行于表面的平面设置的表面埋藏区域（21a）中的指定方向 被分配为电荷的电荷传送方向，并且在与电荷传输方向正交的方向上测量的表面埋藏区域（21a）的宽度的变化中的至少一个和 确定沿着电荷转移方向测量的表面埋藏区域（21a）的杂质浓度分布的变化，使得电荷传输方向上的电场分布是恒定的。

公开(公告)号：US08558293B2

公开(公告)日：2013-10-15

申请号：US13501017

申请日：2010-10-07

申请人： Shoji Kawahito ,  Keita Yasutomi

发明人： Shoji Kawahito ,  Keita Yasutomi

IPC分类号： H01L31/0224

CPC分类号： H01L27/14609 ,  H01L27/14612 ,  H01L27/14689 ,  H04N5/3597

摘要： A semiconductor element includes a base-body region of p-type; a charge-generation buried region of a n-type, implementing a photodiode together with the base-body region, configured to create a first potential valley in the base-body region; an accumulation region of n-type, being buried in a part of the upper portion of the base-body region, configured to create a second potential valley deeper than the first potential valley; a transfer-gate insulation film provided on a surface of the base-body region; a transfer-gate electrode provided on the transfer-gate insulation film, configured to control a potential of a transfer channel formed in the base-body region between the charge-generation buried region and the accumulation region; and a recessed-potential creation mechanism configured to create a stair-like-shaped potential barrier for electronic shuttering.

摘要翻译： 半导体元件包括p型的基体区域; n型的电荷产生掩埋区域，与基体区域一起实现光电二极管，被配置为在基体区域中产生第一电位谷; 埋设在基体区域的上部的一部分中的n型聚集区，被构造成产生比第一电位谷更深的第二电位谷; 设置在所述基体区域的表面上的转印栅绝缘膜; 设置在所述转移栅极绝缘膜上的转移栅电极，被配置为控制形成在所述电荷产生掩埋区域和所述积聚区域之间的所述基体区域中的转移通道的电位; 以及凹陷电位创建机构，被配置为创建用于电子快门的阶梯状势垒。

公开(公告)号：US20130057418A1

公开(公告)日：2013-03-07

申请号：US13599195

申请日：2012-08-30

申请人： Shoji KAWAHITO ,  Sung Wook JUNG ,  Osamu KOBAYASHI ,  Yasuhide SHIMIZU ,  Takahiro MIKI ,  Takashi MORIE ,  Hirotomo ISHII

发明人： Shoji KAWAHITO ,  Sung Wook JUNG ,  Osamu KOBAYASHI ,  Yasuhide SHIMIZU ,  Takahiro MIKI ,  Takashi MORIE ,  Hirotomo ISHII

IPC分类号： H03M1/12

CPC分类号： H03M1/06 ,  H03M1/167

摘要： A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

摘要翻译： 流水线A / D转换器电路包括：采样保持电路，被配置为采样和保持模拟输入信号，并输出采样保持信号;以及A / D转换器电路，包括级联地彼此连接的A / D转换器电路部分， 并以流水线形式执行A / D转换。 每级的流水线A / D转换器电路部分包括子A / D转换器电路，乘法器D / A转换器电路和预充电电路。 子A / D转换电路包括比较器，A / D将输入信号转换为预定位的数字信号; D / A转换器电路，用于对来自子A / D转换器的数字信号进行D / A转换 电路作为参考电压产生的模拟控制信号作为参考值，通过基于模拟控制信号的采样电容采样，保持和放大输入信号。

公开(公告)号：US08289427B2

公开(公告)日：2012-10-16

申请号：US12516635

申请日：2007-11-30

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H04N5/335

CPC分类号： G01S7/4914 ,  G01S17/36 ,  G01S17/89 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/14643 ,  H01L27/14656

摘要： A semiconductor range-finding element encompasses a semiconductor region (1), a light receiving surface-buried region (11a), a first charge-accumulation region (12a), a first charge read-out region (13), a first potential control means (31), a second potential control means (32), a first exhausting-drain region (14) and a third potential control means (33). The signal charges dependent on a delay time of the reflected light are repeatedly transferred from the light receiving surface-buried region (11a) to the first charge-accumulation region (12a) so as to be accumulated as a first signal charge in the first charge-accumulation region (12a) in a first repetition period, all of the signal charges generated by the reflected light are repeatedly transferred from the light receiving surface-buried region (11a) to the first charge-accumulation region (12a) so as to be accumulated as a second signal charge in the first charge-accumulation region (12a) in a second repetition period. A ratio between total quantities of the accumulated first and second signal charges is calculated so as to measure a range to a target sample.

摘要翻译： 半导体测距元件包括半导体区域（1），光接收表面埋入区域（11a），第一电荷累积区域（12a），第一电荷读出区域（13），第一电位控制 装置（31），第二电位控制装置（32），第一排气区域（14）和第三电位控制装置（33）。 取决于反射光的延迟时间的信号电荷从光接收表面埋入区域（11a）重复转移到第一电荷累积区域（12a），以便在第一次充电中被累积为第一信号电荷 - 积累区域（12a），由反射光产生的所有信号电荷从受光面埋藏区域（11a）重复转移到第一电荷蓄积区域（12a），以便成为 在第二重复周期中在第一电荷累积区域（12a）中累积为第二信号电荷。 计算累积的第一和第二信号电荷的总量之间的比率，以便测量到目标样本的范围。

公开(公告)号：US08283913B2

公开(公告)日：2012-10-09

申请号：US13064763

申请日：2011-04-13

申请人： Toru Takahashi ,  Shoji Kawahito

发明人： Toru Takahashi ,  Shoji Kawahito

IPC分类号： G01B7/30

CPC分类号： G01D5/145

摘要： A magnetic array sensor circuit to process an output from a magnetic sensor array including a plurality of magnetic sensor elements arranged in an array. The circuit includes a regulating circuit to reduce an offset variation of the output from the magnetic sensor elements arranged in the array. The regulating circuit includes a control circuit to operate the magnetic sensor element in a linear region. The control circuit includes a reference sensor element in the form of the magnetic sensor element short-circuited between two output terminals, a storage element to store a reference offset value read out from the reference sensor element, and a subtraction circuit to subtract the stored reference offset value from an output of the other magnetic sensor elements.

摘要翻译： 一种用于处理来自包括以阵列布置的多个磁传感器元件的磁传感器阵列的输出的磁阵列传感器电路。 该电路包括调节电路，以减少输出与布置在阵列中的磁传感器元件的偏移偏差。 调节电路包括用于在线性区域中操作磁性传感器元件的控制电路。 控制电路包括在两个输出端子之间短路的磁传感器元件形式的参考传感器元件，存储从参考传感器元件读出的基准偏移值的存储元件，以及减去所存储的参考值的减法电路 偏移值与其他磁传感器元件的输出。

公开(公告)号：US20120193743A1

公开(公告)日：2012-08-02

申请号：US13500331

申请日：2010-10-05

申请人： Shoji Kawahito ,  Tomonari Sawada

发明人： Shoji Kawahito ,  Tomonari Sawada

IPC分类号： H01L27/148 ,  H01L31/102

CPC分类号： H01L27/14609 ,  G01S7/4816 ,  G01S7/4863 ,  H01L27/14603 ,  H01L27/14607 ,  H01L27/14612 ,  H01L27/14656 ,  H04N5/359 ,  H04N5/37452 ,  H04N5/378

摘要： A solid-state imaging device includes a semiconductor region of p-type; a buried region of n-type, configured to serve as a photodiode together with the semiconductor region; a extraction region of n-type, configured to extract charges generated by the photodiode from the buried region, having higher impurity concentration than the buried region; a read-out region of n-type, configured to accumulate charges, which are transferred from the buried region having higher impurity concentration than the buried region; and a potential gradient changing mechanism, configured to control a potential of the channel, and to change a potential gradient of a potential profile from the buried region to the read-out region and a potential gradient of a potential profile from the buried region to the extraction region, so as to control the transferring/extraction of charges.

摘要翻译： 固态成像装置包括p型半导体区域; 配置为与半导体区域一起用作光电二极管的n型掩埋区域; n型的提取区域，被配置为从所述掩埋区域提取由所述光电二极管产生的电荷，其具有比所述掩埋区域更高的杂质浓度; n型的读出区，被配置为累积从掩埋区杂质浓度较高的掩埋区转移的电荷; 以及潜在的梯度改变机构，被配置为控制所述通道的电位，并且改变从所述掩埋区到所述读出区的电位分布的电位梯度，以及从所述埋入区到所述读出区的电位分布的电位梯度 提取区域，以控制收费的转移/提取。

公开(公告)号：US20120127004A1

公开(公告)日：2012-05-24

申请号：US13322375

申请日：2010-05-27

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H03M1/12

CPC分类号： H03M1/0827 ,  H03M1/403

摘要： An A/D conversion integrated circuit including a plurality of A/D converters which can inhibit noises from being propagated by capacitive coupling from a conductor which transmits a digital signal is provided. In an A/D converter 13, an input 15 receives an analog signal to be A/D converted. An output 17 provides at least a part of a digital signal SD having a predetermined number of bits representing the analog signal SA. In response to an analog signal SA, a sub-A/D conversion circuit 19 generates a signal SDP representing one or a plurality of bit values of the digital signal SD and feeds the signal SDP to the output 17. An input 21 a of a control circuit 21 is connected to an output 19a of the sub-A/D conversion circuit 19 and provides a control signal SCONT corresponding to the signal SDP. The control signal SCONT has a waveform including a transition from a voltage level L1 to a voltage level L2 and a transition from the voltage level L2 to the voltage level L1.

摘要翻译： 提供了一种A / D转换集成电路，其包括可抑制噪声通过电容耦合从传输数字信号的导体传播的多个A / D转换器。 在A / D转换器13中，输入端15接收要进行A / D转换的模拟信号。 输出17提供具有表示模拟信号SA的预定数量的位的数字信号SD的至少一部分。 响应于模拟信号SA，子A / D转换电路19产生表示数字信号SD的一个或多个位值的信号SDP，并将信号SDP馈送到输出17.一个输入端21a 控制电路21连接到副A / D转换电路19的输出端19a，并提供对应于信号SDP的控制信号SCONT。 控制信号SCONT具有包括从电压电平L1到电压电平L2的转变以及从电压电平L2向电压电平L1的转变的波形。