公开(公告)号：US08412983B2

公开(公告)日：2013-04-02

申请号：US12585898

申请日：2009-09-28

申请人： Keigo Nakatani

发明人： Keigo Nakatani

IPC分类号： G06F11/00

CPC分类号： G11C29/16 ,  G11C2029/3602

摘要： A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value.

摘要翻译： 存储器测试电路包括计数器电路，其在时钟信号的周期中交替地输出设置为第一设定值或第二设定值的置位信号; OR电路，其计算设定信号和输入的逻辑和 每次当从计数器电路输出设定信号时输出指示设定信号和输入信号的逻辑和的控制信号，以及产生用于使存储器在每一个中操作的测试图案的测试图形生成电路 如果控制信号的设定值是第一设定值，则产生第一周期，或者如果控制信号的设定值是第二设定值，则生成用于使存储器在每个第二周期中操作的测试图案。

公开(公告)号：US07999648B2

公开(公告)日：2011-08-16

申请号：US12711837

申请日：2010-02-24

申请人： Keigo Nakatani ,  Yoshie Nishikawa

发明人： Keigo Nakatani ,  Yoshie Nishikawa

IPC分类号： H01F27/28

CPC分类号： H01F17/04 ,  H01F41/069 ,  Y10T29/49071

摘要： A wire-wound coil has a characteristic impedance that can be flexibly adjusted and can be prevented from varying undesirably. In the coil of the present invention, a primary wire part 18A and a secondary wire part 18B are wound around the surface of a core portion 14 so as to be separated from each other by a fixed distance. At the same time, at least one portion the secondary wire part 18B in a prior turn section 19X and at least one portion of the primary wire part 18A in a subsequent turn section 19Y are in close contact with each other, wherein the wire parts 18A and 18B are wound in different turns and are adjacent to each other on the same surface of the core portion 14. A method for manufacturing the wire-wound coil is also disclosed.

摘要翻译： 绕线线圈具有能够被灵活调节并且可以防止不期望地变化的特性阻抗。 在本发明的线圈中，一次线部分18A和二次线部分18B缠绕在芯部分14的表面上以彼此分开一定距离。 同时，先前的转向部分19X中的次级线部分18B的至少一部分和随后的转向部分19Y中的主线部分18A的至少一部分彼此紧密接触，其中线部分18A 和18B以不同的匝卷绕，并且在芯部分14的相同表面上彼此相邻。还公开了一种用于制造绕线线圈的方法。

公开(公告)号：US08093936B2

公开(公告)日：2012-01-10

申请号：US12560221

申请日：2009-09-15

申请人： Keigo Nakatani

发明人： Keigo Nakatani

IPC分类号： H03K3/00 ,  G06F1/04

CPC分类号： G06F1/12

摘要： According to an aspect of the embodiment, a skew detecting unit includes at least one over delay path or racing path for detecting skew. A clock adjusting unit sets a set value of delay based on the skew detected by the skew detecting unit. A clock cell adjusts delay in a first clock according to the set value of the delay, and outputs the result as a second clock.

摘要翻译： 根据实施例的一个方面，偏斜检测单元包括用于检测偏斜的至少一个过度延迟路径或赛道。 时钟调整单元基于由偏斜检测单元检测到的偏斜来设定延迟的设定值。 时钟单元根据延迟的设定值来调整第一时钟的延迟，并输出结果作为第二时钟。

公开(公告)号：US07804372B2

公开(公告)日：2010-09-28

申请号：US12314388

申请日：2008-12-09

申请人： Keigo Nakatani

发明人： Keigo Nakatani

IPC分类号： H03B5/24

CPC分类号： G01K7/01 ,  G01K7/32 ,  H03K3/0315 ,  H03K5/133

摘要： A ring oscillator includes an odd number of unit circuits connected in series each of which includes an inverter. Each of the unit circuits includes the inverter and a MOSFET. The MOSFET is an FET which is a temperature sensor, and uses a drain-source leakage current in a state that the FET is normally turned off.

摘要翻译： 环形振荡器包括串联连接的奇数个单元电路，每个单元电路包括反相器。 每个单元电路包括反相器和MOSFET。 MOSFET是作为温度传感器的FET，并且在FET正常关断的状态下使用漏极 - 源极泄漏电流。

公开(公告)号：US20100148912A1

公开(公告)日：2010-06-17

申请号：US12711837

申请日：2010-02-24

申请人： Keigo NAKATANI ,  Yoshie NISHIKAWA

发明人： Keigo NAKATANI ,  Yoshie NISHIKAWA

IPC分类号： H01F27/28 ,  H01F41/06

CPC分类号： H01F17/04 ,  H01F41/069 ,  Y10T29/49071

摘要： A wire-wound coil has a characteristic impedance that can be flexibly adjusted and can be prevented from varying undesirably. In the coil of the present invention, a primary wire part 18A and a secondary wire part 18B are wound around the surface of a core portion 14 so as to be separated from each other by a fixed distance. At the same time, at least one portion the secondary wire part 18B in a prior turn section 19X and at least one portion of the primary wire part 18A in a subsequent turn section 19Y are in close contact with each other, wherein the wire parts 18A and 18B are wound in different turns and are adjacent to each other on the same surface of the core portion 14. A method for manufacturing the wire-wound coil is also disclosed.

摘要翻译： 绕线线圈具有能够被灵活调节并且可以防止不期望地变化的特性阻抗。 在本发明的线圈中，一次线部分18A和二次线部分18B缠绕在芯部分14的表面上以彼此分开一定距离。 同时，先前的转向部分19X中的次级线部分18B的至少一部分和随后的转向部分19Y中的主线部分18A的至少一部分彼此紧密接触，其中线部分18A 和18B以不同的匝卷绕，并且在芯部分14的相同表面上彼此相邻。还公开了一种用于制造绕线线圈的方法。

公开(公告)号：US20100066424A1

公开(公告)日：2010-03-18

申请号：US12560221

申请日：2009-09-15

申请人： Keigo NAKATANI

发明人： Keigo NAKATANI

IPC分类号： H03K5/13

CPC分类号： G06F1/12

摘要： According to an aspect of the embodiment, a skew detecting unit includes at least one over delay path or racing path for detecting skew. A clock adjusting unit sets a set value of delay based on the skew detected by the skew detecting unit. A clock cell adjusts delay in a first clock according to the set value of the delay, and outputs the result as a second clock.

摘要翻译： 根据实施例的一个方面，偏斜检测单元包括用于检测偏斜的至少一个过度延迟路径或赛道。 时钟调整单元基于由偏斜检测单元检测到的偏斜来设定延迟的设定值。 时钟单元根据延迟的设定值来调整第一时钟的延迟，并输出结果作为第二时钟。

公开(公告)号：US20100023809A1

公开(公告)日：2010-01-28

申请号：US12585898

申请日：2009-09-28

申请人： Keigo Nakatani

发明人： Keigo Nakatani

IPC分类号： G06F11/00

CPC分类号： G11C29/16 ,  G11C2029/3602

摘要： A memory test circuit includes a counter circuit that outputs a set signal that is set to the first set value or the second set value alternately in a cycle of the clock signal, an OR circuit that calculates a logical sum of the set signal and the input signal each time when the set signal is output from the counter circuit and outputs a control signal indicating the logical sum of the set signal and the input signal, and a test pattern generation circuit that generates the test pattern for causing the memory to operate in each first cycle if a set value of the control signal is the first set value, or generates the test pattern for causing the memory to operate in each second cycle if the set value of the control signal is the second set value.

摘要翻译： 存储器测试电路包括计数器电路，其在时钟信号的周期中交替地输出设置为第一设定值或第二设定值的置位信号; OR电路，其计算设定信号和输入的逻辑和 每次当从计数器电路输出设定信号时输出指示设定信号和输入信号的逻辑和的控制信号，以及产生用于使存储器在每一个中操作的测试图案的测试图形生成电路 如果控制信号的设定值是第一设定值，则产生第一周期，或者如果控制信号的设定值是第二设定值，则生成用于使存储器在每个第二周期中操作的测试图案。