公开(公告)号：US6094734A

公开(公告)日：2000-07-25

申请号：US917020

申请日：1997-08-22

申请人： Ray Beffa ,  Eugene H. Cloud ,  Leland R. Nevill ,  Ken Waller ,  Warren M. Farnworth

发明人： Ray Beffa ,  Eugene H. Cloud ,  Leland R. Nevill ,  Ken Waller ,  Warren M. Farnworth

IPC分类号： G11C29/02 ,  G11C29/12 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/5004

摘要： A test arrangement for a memory device wherein the equilibration voltage DVC2 is adjusted up or down relative to a nominal value and coupled to one of the bitlines of the paired bitlines of the memory array, while the equilibrating circuit is held disabled, and then the sense amplifiers are used to pull the bitlines to logic 1 and logic 0 levels initializing the bitlines to test data. Appropriate word lines are fired to copy the test data to some or all of the other rows of the memory array, allowing memory tests to be conducted. In another embodiment, a fixed voltage is applied to one of the bitlines of individual bitlines pairs and the sense amplifiers are used to pull the paired bitlines to the correct voltage. In a further embodiment, fixed voltages Vcc and ground are applied to the bitlines of each bitline pair with the sense amplifier being held disabled. The test arrangement can be implemented as a self-test feature for the memory device.

摘要翻译： 一种用于存储器件的测试装置，其中平衡电压DVC2相对于标称值被上调或下调并耦合到存储器阵列的成对位线的位线之一，而平衡电路被保持禁用，然后感测 放大器用于将位线拉到逻辑1和逻辑0电平初始化位线以测试数据。 触发适当的字线将测试数据复制到存储器阵列的其他行的一些或全部，以进行内存测试。 在另一个实施例中，将固定电压施加到单个位线对的位线之一，并且读出放大器用于将成对的位线拉到正确的电压。 在另一个实施例中，将固定电压Vcc和接地施加到每个位线对的位线，使读出放大器保持禁用。 测试装置可以作为存储器件的自检特征来实现。

公开(公告)号：US6003149A

公开(公告)日：1999-12-14

申请号：US917215

申请日：1997-08-22

申请人： Leland R. Nevill ,  Ray Beffa ,  Ken Waller ,  Eugene H. Cloud ,  Warren M. Farnworth

发明人： Leland R. Nevill ,  Ray Beffa ,  Ken Waller ,  Eugene H. Cloud ,  Warren M. Farnworth

IPC分类号： G11C29/34 ,  G11C29/00

CPC分类号： G11C29/34

摘要： A method of testing a memory array is disclosed, the method comprising writing a test pattern to the memory array in as few as one or two RAS cycles by first activating the input/output data lines and then selectively activating multiple rows and columns. The method can be used with a variety of test environments. For example, the disclosed method may be implemented in testing using automated test equipment, and may also be incorporated in devices having built-in self-test circuitry. The disclosed method reduces the time required to test the memory array with minimal additional circuitry and no encroachment on valuable die real estate.

摘要翻译： 公开了一种测试存储器阵列的方法，所述方法包括通过首先激活输入/输出数据线然后选择性地激活多个行和列来将测试图案写入至少一个或两个RAS周期中的存储器阵列。 该方法可用于各种测试环境。 例如，所公开的方法可以在使用自动测试设备的测试中实现，并且还可以并入具有内置自测电路的设备中。 所公开的方法减少了以最小的附加电路测试存储器阵列所需的时间，并且不侵占有价值的裸片的不动产。

公开(公告)号：US5999480A

公开(公告)日：1999-12-07

申请号：US167259

申请日：1998-10-06

申请人： Adrian Ong ,  Paul S. Zagar ,  Troy Manning ,  Brent Keeth ,  Ken Waller

发明人： Adrian Ong ,  Paul S. Zagar ,  Troy Manning ,  Brent Keeth ,  Ken Waller

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/36 ,  G11C8/00

CPC分类号： G11C29/785 ,  G11C11/4096 ,  G11C29/80 ,  G11C29/88 ,  G11C5/025 ,  G11C7/10 ,  G11C29/36

摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancyis disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. A hierarchical data path is provided wherein a plurality of multiplexers are distributed throughout each SAB, these multiplexers functioning to selectively couple sense amplifier output signals to local data I/O lines associated with each SAB. In one embodiment, the data path multiplexers are physically disposed within gaps defined by adjacent ones of the local row address decoders distributed throughout each SAB.

摘要翻译： 一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，其集合和/或单独证明在所公开的诸如密度，功耗，速度和冗余度之类的考虑方面是有益和有利的。 该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。 顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。 列选择线来自列块，并在每个象限的宽度上左右延伸。 每个PAB包括八个基本相同的1M位子阵列块（SAB）。 与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。 提供了分层数据路径，其中多个复用器分布在每个SAB中，这些多路复用器用于选择性地将感测放大器输出信号耦合到与每个SAB相关联的本地数据I / O线。 在一个实施例中，数据路径多路复用器物理地布置在分布在每个SAB中的相邻的本地行地址解码器限定的间隙内。

公开(公告)号：US5901105A

公开(公告)日：1999-05-04

申请号：US869035

申请日：1997-06-05

申请人： Adrian E Ong ,  Paul S. Zagar ,  Troy Manning ,  Brent Keeth ,  Ken Waller

发明人： Adrian E Ong ,  Paul S. Zagar ,  Troy Manning ,  Brent Keeth ,  Ken Waller

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/36 ,  G11C8/00

CPC分类号： G11C29/785 ,  G11C11/4096 ,  G11C29/80 ,  G11C29/88 ,  G11C5/025 ,  G11C7/10 ,  G11C29/36

摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancy is disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1 Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. Various pre- and/or post-packaging options are provided for enabling a large degree of versatility, redundancy, and economy of design. Programmable options of the disclosed device are programmable by means of both laser fuses and electrical fuses. In the RAS chain, circuitry is provided for simulating the RC time constant behavior of word lines and digit lines during memory accesses, such that memory access cycle time can be optimized. Test data compression circuitry optimizes the process of testing each cell in the array. On-chip topology circuitry simplifies the testing of the device.

摘要翻译： 公开了一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，它们集中和/或单独地证明了在诸如密度，功耗，速度和冗余度之类的考虑方面是有利和有利的。 该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。 顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。 列选择线来自列块，并在每个象限的宽度上左右延伸。 每个PAB包括八个基本上相同的1兆位子阵列块（SAB）。 与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。 提供了各种前置和/或后封装选项，以实现大量多功能性，冗余性和设计经济性。 所公开的设备的可编程选项可通过激光熔丝和电熔丝两者来编程。 在RAS链中，提供电路用于在存储器访问期间模拟字线和数字线的RC时间常数行为，使得可以优化存储器访问周期时间。 测试数据压缩电路优化了测试阵列中每个单元的过程。 片上拓扑电路简化了器件的测试。