公开(公告)号：US06622270B2

公开(公告)日：2003-09-16

申请号：US10013684

申请日：2001-12-13

申请人： Ray Beffa

发明人： Ray Beffa

IPC分类号： G11C2900

CPC分类号： G11C29/08 ,  G01R31/318371 ,  G01R31/319 ,  G06F11/006 ,  G11C29/10 ,  G11C29/26 ,  G11C29/44

摘要： A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.

公开(公告)号：US06347386B1

公开(公告)日：2002-02-12

申请号：US09612098

申请日：2000-07-07

申请人： Ray Beffa

发明人： Ray Beffa

IPC分类号： G11C2900

CPC分类号： G11C29/08 ,  G01R31/318371 ,  G01R31/319 ,  G06F11/006 ,  G11C29/10 ,  G11C29/26 ,  G11C29/44

摘要： A method and apparatus for testing semiconductor memory chips, such as DRAMs, having a plurality of memory cells or bits. Each memory chip has a unique identifier stored in a database. Tests are performed on the memory chips and when a memory chip fails a test, the memory chip is placed in a repair bin and a test identifier is stored in the database in association with the memory chip identifier. In order to repair the memory chip, failed tests are read out of the database and such tests are again performed on the failed memory chip in order to determine which memory cell in the memory chip is faulty. The failed memory cells are then repaired.

摘要翻译： 一种用于测试诸如DRAM的半导体存储器芯片的方法和装置，其具有多个存储单元或位。 每个存储器芯片具有存储在数据库中的唯一标识符。 对存储器芯片进行测试，并且当存储器芯片未通过测试时，将存储器芯片放置在修理槽中，并且与存储器芯片标识符相关联地将测试标识符存储在数据库中。 为了修复存储器芯片，从数据库读出失败的测试，并且在故障存储器芯片上再次执行这样的测试，以便确定存储器芯片中的哪个存储器单元是有故障的。 然后修复失败的内存单元。

公开(公告)号：US5966025A

公开(公告)日：1999-10-12

申请号：US956095

申请日：1997-10-23

申请人： Ray Beffa

发明人： Ray Beffa

IPC分类号： G01R31/12 ,  G01R31/27 ,  G01R31/28 ,  G11C29/02 ,  G11C29/46 ,  G11C29/50 ,  G01R31/26

CPC分类号： G11C29/50008 ,  G01R31/12 ,  G01R31/275 ,  G01R31/2884 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C11/401 ,  G11C2029/0403 ,  G11C2029/5004 ,  G11C29/46

摘要： A semiconductor memory device includes a die having a semiconductor memory circuit formed thereon and a plurality of pads at the periphery of the die that are electrically coupled to the circuit. Electrically conductive leads have a pin end for external coupling, and a free end electrically connected by bond wires to certain pads on the die. An encapsulating material such as epoxy encapsulates the die, bond wires and free ends of the leads to form a packaged chip. A superfluous lead such as an address lead unused during testing, redundant voltage supply lead or non-connected lead is coupled, by means of a bond wire, to a pad that, in turn, is coupled through a switching transistor to a common cell plate or DVC2 node for all storage capacitors in the memory circuit. External power can thereby be provided to the DVC2 node to simultaneously apply a high voltage to this node of all capacitors during stress testing of the chip. The arrangement allows for efficient testing for dielectric defects in the capacitors while the die is in packaged chip form.

公开(公告)号：US5898629A

公开(公告)日：1999-04-27

申请号：US915757

申请日：1997-08-21

申请人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

发明人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

IPC分类号： G11C29/50 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C11/401 ,  G11C29/56

摘要： A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

摘要翻译： 能够在晶片烧录期间使用的存储器自应力模式，例如用于动态随机存取存储器（DRAM）集成电路。 将老化的电源电压和接地电压传送到多个存储单元存储电容器的公共节点以及耦合到位线的均衡节点。 全行高测试在二进制低逻辑电平和二进制高逻辑电平之间循环字线，从而通过施加不同极性的应力电压来强调存储器单元存储电容器的电介质。 半行高测试周期交替字线序列的字线，从而强调相邻字线之间的不期望的短路连接。

公开(公告)号：US06233185B1

公开(公告)日：2001-05-15

申请号：US09257403

申请日：1999-02-25

申请人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

发明人： Ray Beffa ,  Leland R. Nevill ,  Warren M. Farnworth ,  Eugene H. Cloud ,  William K. Waller

IPC分类号： G11C1300

CPC分类号： G11C29/006 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/1202

摘要： A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.

摘要翻译： 能够在晶片烧录期间使用的存储器自应力模式，例如用于动态随机存取存储器（DRAM）集成电路。 将老化的电源电压和接地电压传送到多个存储单元存储电容器的公共节点以及耦合到位线的均衡节点。 全行高测试在二进制低逻辑电平和二进制高逻辑电平之间循环字线，从而通过施加不同极性的应力电压来强调存储器单元存储电容器的电介质。 半行高测试周期交替字线序列的字线，从而强调相邻字线之间的不期望的短路连接。

公开(公告)号：US06181154B2

公开(公告)日：2001-01-30

申请号：US09237998

申请日：1999-01-26

申请人： Ray Beffa

发明人： Ray Beffa

IPC分类号： G01R3126

CPC分类号： G11C29/50008 ,  G01R31/12 ,  G01R31/275 ,  G01R31/2884 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2029/5004

摘要： A semiconductor memory device includes a die having a semiconductor memory circuit formed thereon and a plurality of pads at the periphery of the die that are electrically coupled to the circuit. Electrically conductive leads have a pin end for external coupling, and a free end electrically connected by bond wires to certain pads on the die. An encapsulating material such as epoxy encapsulates the die, bond wires and free ends of the leads to form a packaged chip. A superfluous lead such as an address lead unused during testing, redundant voltage supply lead or non-connected lead is coupled, by means of a bond wire, to a pad that, in turn, is coupled through a switching transistor to a common cell plate or DVC2 node for all storage capacitors in the memory circuit. External power can thereby be provided to the DVC2 node to simultaneously apply a high voltage to this node of all capacitors during stress testing of the chip. The arrangement allows for efficient testing for dielectric defects in the capacitors while the die is in packaged chip form.

摘要翻译： 半导体存储器件包括具有形成在其上的半导体存储电路和与该电路电连接的管芯外围的多个焊盘的裸片。 导电引线具有用于外部耦合的引脚端，并且自由端通过接合线电连接到管芯上的某些焊盘。 诸如环氧树脂的封装材料封装芯片，接合线和导线的自由端以形成封装的芯片。 诸如测试期间未使用的地址引线的多余导线，冗余电压供应引线或非连接引线通过接合线耦合到焊盘，焊盘又通过开关晶体管耦合到公共单元板 或DVC2节点，用于存储器电路中的所有存储电容器。 因此，可以在DVC2节点提供外部功率，以在芯片的应力测试期间同时向所有电容器的该节点施加高电压。 该装置允许有效测试电容器中的电介质缺陷，同时芯片处于封装芯片形式。

公开(公告)号：US6058056A

公开(公告)日：2000-05-02

申请号：US70558

申请日：1998-04-30

申请人： Ray Beffa ,  Leland R. Nevill ,  Neil L. Hansen ,  Eugene H. Cloud

发明人： Ray Beffa ,  Leland R. Nevill ,  Neil L. Hansen ,  Eugene H. Cloud

IPC分类号： G11C7/22 ,  G11C29/40 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C29/40

摘要： A test circuit detects defective memory cells in a memory device. The test circuit includes a test mode terminal adapted to receive a test mode signal. An error detection circuit includes a plurality of inputs and an output, each input coupled to some of the plurality of memory cells. The error detection circuit develops an active error signal on an output when the binary value of data on at least one input is different from predetermined binary values of data. A control circuit is coupled to the test mode terminal, the error detection circuit, and the memory cells. The control circuit is operable responsive to the test mode signal being active to apply the data of accessed memory cells to the associated inputs of the error detection circuit such that the error detection circuit drives the error signal active when the binary value of the data stored in at least one accessed memory cell is different from predetermined binary values.

摘要翻译： 测试电路检测存储器件中的有缺陷的存储单元。 测试电路包括适于接收测试模式信号的测试模式终端。 误差检测电路包括多个输入和输出，每个输入耦合到多个存储单元中的一些。 当至少一个输入上的数据的二进制值不同于数据的预定二进制值时，错误检测电路在输出上产生有效的误差信号。 控制电路耦合到测试模式端子，误差检测电路和存储器单元。 控制电路可以响应于测试模式信号被激活以将访问的存储器单元的数据应用于错误检测电路的相关输入，使得当存储在数据中的数据的二进制值时，错误检测电路驱动该误差信号有效 至少一个被访问的存储单元与预定的二进制值不同。

公开(公告)号：US5754486A

公开(公告)日：1998-05-19

申请号：US808391

申请日：1997-02-28

申请人： Leland R. Nevill ,  Ray Beffa ,  Warren M. Farnworth ,  Gene Cloud

发明人： Leland R. Nevill ,  Ray Beffa ,  Warren M. Farnworth ,  Gene Cloud

IPC分类号： G11C7/06 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/10 ,  G11C29/14 ,  G11C29/34 ,  G11C29/36 ,  G11C29/50 ,  G11C29/00

CPC分类号： G11C29/10 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/14 ,  G11C29/34 ,  G11C29/36 ,  G11C29/50 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401

摘要： A sense amplifier senses and stores data from a memory cell in an array of memory cells arranged in rows and columns. The sense amplifier includes a sense circuit having a pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and in response to the sensed voltage differential drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states. An isolation circuit is coupled between the pair of first and second complementary digit lines of the sense amplifier and a pair of first and second complementary digit lines associated with a column of memory cells. The isolation circuit is operable to couple the first complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells and the second complementary digit line of the sense amplifier to the secondary complementary digit line of the column of memory cells. A switch circuit is operable to couple the first complementary digit line of the sense amplifier to the second complementary digit line of the column of memory cells, and the second complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells. An equilibration circuit is coupled between the pair of complementary digit lines of the column of memory cells and is operable to equalize the voltage level on the digit lines to a predetermined level.

公开(公告)号：US5657284A

公开(公告)日：1997-08-12

申请号：US531226

申请日：1995-09-19

申请人： Ray Beffa

发明人： Ray Beffa

IPC分类号： G11C29/34 ,  G11C29/50 ,  G11C13/00 ,  G11C5/14

CPC分类号： G11C29/34 ,  G11C29/50 ,  G11C11/401

摘要： A semiconductor memory device includes a die having a semiconductor memory circuit formed thereon and a plurality of pads at the periphery of the die that are electrically coupled to the circuit. Electrically conductive leads have a pin end for external coupling, and a free end electrically connected by bond wires to certain pads on the die. An encapsulating material such as epoxy encapsulates the die, bond wires and free ends of the leads to form a packaged chip. A superfluous lead such as a redundant voltage supply lead or non-connected lead is coupled, by means of a bond wire, to a pad that, in turn, is coupled to a voltage boosting circuit on the die. The voltage boosting circuit is coupled to row lines in the semiconductor memory circuit to provide boosted voltage thereto. External power can thereby be provided to the row lines, through the voltage boosting circuits, to simultaneously enable at least half of the row lines during stress testing of the chip. The arrangement allows for efficient testing for cell-to-cell defects while the die is in packaged chip form.

摘要翻译： 半导体存储器件包括具有形成在其上的半导体存储电路和与该电路电连接的芯片周边的多个焊盘的裸片。 导电引线具有用于外部耦合的引脚端，并且自由端通过接合线电连接到管芯上的某些焊盘。 诸如环氧树脂的封装材料封装芯片，接合线和导线的自由端以形成封装的芯片。 诸如冗余电压源引线或非连接引线的多余引线通过接合线耦合到焊盘，焊盘又连接到管芯上的升压电路。 升压电路耦合到半导体存储器电路中的行线以向其提供升压电压。 由此，可以通过升压电路将行电源提供外部电力，以在芯片的应力测试期间同时使能行行的至少一半。 该装置允许在芯片处于封装芯片形式的情况下有效测试细胞间细胞缺陷。

公开(公告)号：US20050174871A1

公开(公告)日：2005-08-11

申请号：US11101801

申请日：2005-04-07

申请人： Russell Meyer ,  Ray Beffa

发明人： Russell Meyer ,  Ray Beffa

IPC分类号： G11C7/04 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40626 ,  G11C11/406

摘要： The illustrated embodiments relate to a process for improving retention time of a set of integrated circuit devices. The process comprises placing the set of integrated circuit devices in a reverse bias condition, and elevating the surrounding temperature of the set of integrated circuit devices for a predetermined period of time.

摘要翻译： 所示实施例涉及一种用于改善一组集成电路器件的保持时间的方法。 该过程包括将集成电路器件集合放置在反向偏置状态，并且将集成电路器件集合的周围温度提高预定时间段。