Apparatus, system and method capable of clock noise mitigation using a frequency adaptive process
    7.
    发明授权
    Apparatus, system and method capable of clock noise mitigation using a frequency adaptive process 有权
    能够使用频率自适应处理来对噪声进行减噪的装置,系统和方法

    公开(公告)号:US07279989B2

    公开(公告)日:2007-10-09

    申请号:US11169365

    申请日:2005-06-28

    IPC分类号: H03L7/18 H04B1/10

    CPC分类号: H03L7/18

    摘要: An embodiment of the present invention provides an apparatus, comprising an oscillator capable of generating a clock signal, wherein said apparatus is capable of clock noise mitigation using a frequency adaptive algorithm, technique, process or system. And wherein said oscillator may be a voltage controlled oscillator (VCO) operating near a desired frequency used to generate an output signal. The clock noise mitigation may accomplished by portion of said VCO signal being fed into a first dividing circuit capable of dividing by a given number M, and a second dividing circuit, N, wherein said first and second dividing circuits may be capable of producing a signal close to the frequency of a reference oscillator, said VCO signal may then be compared via a phase comparator to a reference frequency and wherein the phase comparator signal may then be fed back to the VCO such that its frequency will “lock” to said reference oscillator. The M and N dividers may be set to enable the frequency increments to be as small as desired and may be dynamically programmable. Depending on the communication channels being used, the frequency of the clock may modified either up or down to avoid interference.

    摘要翻译: 本发明的一个实施例提供了一种装置,包括能够产生时钟信号的振荡器,其中所述装置能够使用频率自适应算法,技术,过程或系统进行时钟噪声抑制。 并且其中所述振荡器可以是在用于产生输出信号的期望频率附近操作的压控振荡器(VCO)。 时钟噪声减轻可以通过将所述VCO信号的一部分馈送到能够除以给定数量M的第一分频电路和第二分频电路N来实现,其中所述第一和第二分频电路可以产生信号 接近参考振荡器的频率,然后可以将所述VCO信号经由相位比较器与参考频率进行比较,并且其中相位比较器信号然后可被反馈到VCO,使得其频率将“锁定”到所述参考振荡器 。 可以将M和N分频器设置为使得频率增量能够根据需要变得小,并且可以是动态可编程的。 根据正在使用的通信信道,时钟的频率可以上下修改,以避免干扰。