公开(公告)号：US06763471B1

公开(公告)日：2004-07-13

申请号：US09723386

申请日：2000-11-28

申请人： Koichiro Aoyama

发明人： Koichiro Aoyama

IPC分类号： G06F132

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/3203 ,  Y02D10/126

摘要： A central processing unit, a read only memory, a random access memory, an oscillator for supplying a clock signal to the central processing unit, a peripheral circuit and a control circuit are provided. The control circuit supplies a first voltage to the central processing unit, the read only memory, the random access memory and the peripheral circuit in synchronization with rising/falling of the clock signal, and supplies a second voltage to the central processing unit with passage of predetermined time after the rising/falling of the clock signal. The first voltage enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to change their operations. The second voltage is lower than the first voltage, and enables the central processing unit, the read only memory, the random access memory and the peripheral circuit to maintain their operations.

摘要翻译： 提供了中央处理单元，只读存储器，随机存取存储器，用于向中央处理单元提供时钟信号的振荡器，外围电路和控制电路。 控制电路与时钟信号的上升/下降同步地向中央处理单元，只读存储器，随机存取存储器和外围电路提供第一电压，并且通过第二电压通过中央处理单元 在时钟信号的上升/下降之后的预定时间。 第一电压使得中央处理单元，只读存储器，随机存取存储器和外围电路改变其操作。 第二电压低于第一电压，并且使得中央处理单元，只读存储器，随机存取存储器和外围电路能够维持它们的操作。

公开(公告)号：US5225715A

公开(公告)日：1993-07-06

申请号：US879310

申请日：1992-05-07

申请人： Takehiko Mori ,  Koichiro Aoyama

发明人： Takehiko Mori ,  Koichiro Aoyama

IPC分类号： H03K5/1252 ,  H03K5/153

CPC分类号： H03K5/153 ,  H03K5/1252

摘要： A pulse discriminating circuit discriminates narrow input pulses from an input pulse signal for eliminating output pulses corresponding to the narrow pulses from an output pulse signal thereof, and comprises a delay unit supplied with the input pulse signal for introducing predetermined time delay into propagation of the input pulse signal in synchronism with a two-phase clock signal, and an eliminating unit responsive to output signals of the delay unit and operative to produce the output pulse signal consisting of output pulses corresponding to wide input pulses, wherein the delay unit comprises early stages responsive to the two-phase clock signal for transferring the input pulse signal, and later stages responsive to a transfer signal lower in frequency than the two-phase clock signal for transferring the input pulse signal so that the predetermined time delay is prolonged without increase the stages of the delay unit.

公开(公告)号：US5359636A

公开(公告)日：1994-10-25

申请号：US914299

申请日：1992-07-15

申请人： Koichiro Aoyama

发明人： Koichiro Aoyama

IPC分类号： G06F1/24 ,  G06F15/78 ,  G11C19/00 ,  H03K21/02 ,  H03K23/42

CPC分类号： G11C19/00

摘要： A register control circuit has a plurality of registers, a control circuit for producing clock signals, and a logic circuit for producing latch clocks based on a reset signal and the clock signals. A shift data is inputted to a first one of the plurality of registers through a 2-input AND gate. The latch clocks are forced to become active simultaneously under a state in which an input to the first stage register being controlled to "0". The shift register is initialized in such a way that a "0" input is sequentially transferred from the first stage register to the final stage register. The shift register can be formed without the need of registers having reset inputs and initialized speedily, while keeping the increase in the device elements at the minimum.

摘要翻译： 寄存器控制电路具有多个寄存器，用于产生时钟信号的控制电路和用于根据复位信号和时钟信号产生锁存时钟的逻辑电路。 移位数据通过2输入与门输入到多个寄存器的第一个寄存器。 在第一级寄存器的输入被控制为“0”的状态下，锁存时钟被强制同时变为有效。 移位寄存器被初始化为使得“0”输入从第一级寄存器顺序传送到最后级寄存器。 可以形成移位寄存器，而不需要具有复位输入和快速初始化的寄存器，同时将器件元件的增加保持在最小。