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1.发明授权High-speed mixed analog/digital PRML data detection and clock recovery apparatus and method for data storage 有权高速混合模拟/数字PRML数据检测和时钟恢复装置和数据存储方法公开(公告)号：US07616547B2
公开(公告)日：2009-11-10
申请号：US11059458
申请日：2005-02-16
Applicant: Jeong-won Lee , Jung-hyun Lee , Jae-wook Lee , Jung-eun Lee , Konakov Maxim
Inventor： Jeong-won Lee , Jung-hyun Lee , Jae-wook Lee , Jung-eun Lee , Konakov Maxim
CPC classification number: G11B20/10055 , G11B20/10009 , G11B20/10111 , G11B20/10296 , G11B20/1426
Abstract: A high-speed mixed analog/digital PRML data detection and clock recovery apparatus and method. The high-speed mixed analog/digital PRML data detection and clock recovery apparatus includes a variable gain amplifier, an analog equalizer, an analog-to-digital (A/D) converter, a DC offset remover, a level error detector, a Viterbi decoder, and an adaptive digital controller. The adaptive digital controller separately stores the level error values by predetermined frequencies, calculates predetermined coefficient values by each frequency component based on the level error values, and D/A-converts and applies the calculated predetermined coefficient values to the variable gain amplifier and the analog equalizer.
Abstract translation: 高速混合模/数字PRML数据检测和时钟恢复装置及方法。 高速混合模拟/数字PRML数据检测和时钟恢复装置包括可变增益放大器，模拟均衡器，模数（A / D）转换器，DC偏移去除器，电平误差检测器，Viterbi 解码器和自适应数字控制器。 自适应数字控制器分别按预定频率存储电平误差值，并根据电平误差值计算每个频率分量的预定系数值，并对所计算出的预定系数值进行D / A转换并将其计算给可变增益放大器和模拟 均衡器
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2.发明申请High-speed mixed analog/digital PRML data detection and clock recovery apparatus and method for data storage 有权高速混合模拟/数字PRML数据检测和时钟恢复装置和数据存储方法公开(公告)号：US20050180287A1
公开(公告)日：2005-08-18
申请号：US11059458
申请日：2005-02-16
Applicant: Jeong-won Lee , Jung-hyun Lee , Jae-wook Lee , Jung-eun Lee , Konakov Maxim
Inventor： Jeong-won Lee , Jung-hyun Lee , Jae-wook Lee , Jung-eun Lee , Konakov Maxim
CPC classification number: G11B20/10055 , G11B20/10009 , G11B20/10111 , G11B20/10296 , G11B20/1426
Abstract: A high-speed mixed analog/digital PRML data detection and clock recovery apparatus and method. The high-speed mixed analog/digital PRML data detection and clock recovery apparatus includes a variable gain amplifier, an analog equalizer, an analog-to-digital (A/D) converter, a DC offset remover, a level error detector, a Viterbi decoder, and an adaptive digital controller. The adaptive digital controller separately stores the level error values by predetermined frequencies, calculates predetermined coefficient values by each frequency component based on the level error values, and D/A-converts and applies the calculated predetermined coefficient values to the variable gain amplifier and the analog equalizer.
Abstract translation: 高速混合模/数字PRML数据检测和时钟恢复装置及方法。 高速混合模拟/数字PRML数据检测和时钟恢复装置包括可变增益放大器，模拟均衡器，模数（A / D）转换器，DC偏移去除器，电平误差检测器，Viterbi 解码器和自适应数字控制器。 自适应数字控制器分别按预定频率存储电平误差值，并根据电平误差值计算每个频率分量的预定系数值，并对所计算出的预定系数值进行D / A转换并将其计算给可变增益放大器和模拟 均衡器
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