公开(公告)号：US08422669B2

公开(公告)日：2013-04-16

申请号：US12891467

申请日：2010-09-27

申请人： Dai Yamamoto ,  Kouichi Itoh

发明人： Dai Yamamoto ,  Kouichi Itoh

IPC分类号： H04K1/00

CPC分类号： G06F7/725 ,  H04L9/003 ,  H04L9/3066

摘要： An apparatus includes a data storage to store a window table storing a table value with an index value mapped to the table value, the index value having same number of bits as a window width, the table value being a sum of a basic table value and a non-zero table correction value, the basic table value being obtained by multiplying a point G on an elliptic curve. An arithmetic processor generates the index value by reading from a scalar value at a bit position assigned to each bit of the window with the window being shifted, reads the table value from the window table according to the index value, and performs a doubling operation and an addition operation using the read table value. A corrector performs a correction on arithmetic results with a specific correction value responsive to the table correction value.

摘要翻译： 一种装置，包括：数据存储器，用于存储存储具有映射到表格值的索引值的表格值的窗口表，所述索引值具有与窗口宽度相同的位数，所述表格值是基本表格值和 非零表校正值，通过将点G乘以椭圆曲线获得的基本表值。 算术处理器通过从分配给窗口移位的窗口的每个位的位位置的标量值读取生成索引值，根据索引值从窗口表读取表格值，并执行加倍操作，并且 使用读表值的加法运算。 校正器根据表校正值对具有特定校正值的算术结果进行校正。

公开(公告)号：US08111827B2

公开(公告)日：2012-02-07

申请号：US12612290

申请日：2009-11-04

申请人： Dai Yamamoto ,  Kouichi Itoh

发明人： Dai Yamamoto ,  Kouichi Itoh

IPC分类号： H04K1/00 ,  H04K1/04 ,  H04K1/06 ,  H04L9/00 ,  H04L9/28

CPC分类号： H04L9/0625 ,  H04L2209/122

摘要： A cryptographic processing apparatus for performing arithmetic operation on an FL function and an FL−1 function in a cryptographic process includes a first arithmetic gate is configured to receive a first input bit string and a first extended key bit string, a first XOR gate configured to receive an output of the first arithmetic gate and a second input bit string, a second arithmetic gate configured to receive an output of the first XOR gate and a second extended key bit string, a second XOR gate configured to receive an output of the second arithmetic gate and the first input bit string, a third arithmetic gate configured to receive an output of the second XOR gate and the first extended key bit string, and a third XOR gate configured to receive an output of the third arithmetic gate and an output of the first XOR gate.

摘要翻译： 一种用于在密码处理中对FL功能和FL-1功能进行算术运算的加密处理装置，包括：第一运算门，被配置为接收第一输入位串和第一扩展密钥位串，第一XOR门被配置为 接收第一算术门和第二输入比特串的输出，第二运算门，被配置为接收第一异或门和第二扩展密钥位串的输出;第二异或门，被配置为接收第二算术的输出 栅极和第一输入位串，第三运算门，被配置为接收第二异或门和第一扩展密钥位串的输出;以及第三异或门，被配置为接收第三运算门的输出， 第一个XOR门。

公开(公告)号：US20110075836A1

公开(公告)日：2011-03-31

申请号：US12891467

申请日：2010-09-27

申请人： Dai YAMAMOTO ,  Kouichi Itoh

发明人： Dai YAMAMOTO ,  Kouichi Itoh

IPC分类号： H04L9/28

CPC分类号： G06F7/725 ,  H04L9/003 ,  H04L9/3066

摘要： An apparatus includes a data storage to store a window table storing a table value with an index value mapped to the table value, the index value having same number of bits as a window width, the table value being a sum of a basic table value and a non-zero table correction value, the basic table value being obtained by multiplying a point G on an elliptic curve. An arithmetic processor generates the index value by reading from a scalar value at a bit position assigned to each bit of the window with the window being shifted, reads the table value from the window table according to the index value, and performs a doubling operation and an addition operation using the read table value. A corrector performs a correction on arithmetic results with a specific correction value responsive to the table correction value.

摘要翻译： 一种装置，包括：数据存储器，用于存储存储具有映射到表格值的索引值的表格值的窗口表，所述索引值具有与窗口宽度相同的位数，所述表格值是基本表格值和 非零表校正值，通过将点G乘以椭圆曲线获得的基本表值。 算术处理器通过从分配给窗口移位的窗口的每个位的位位置的标量值读取生成索引值，根据索引值从窗口表读取表格值，并执行加倍操作，并且 使用读表值的加法运算。 校正器根据表校正值对具有特定校正值的算术结果进行校正。

公开(公告)号：US20110013770A1

公开(公告)日：2011-01-20

申请号：US12890212

申请日：2010-09-24

申请人： KOUICHI ITOH

发明人： KOUICHI ITOH

IPC分类号： H04L9/28

CPC分类号： G06F7/723 ,  G06F2207/7219 ,  H04L9/003 ,  H04L9/302

摘要： Based on an encrypting method for performing an exponential remainder calculation y=ad (mod n) from an u-bit exponent d=(du−1, . . . , d0)2, input data a, and a modulo n, calculating a′=a2(mod n) is performed first. Next, calculating y=(a′)f(mod n) is performed on f=(du−1, du−2, . . . , d1)2. Then, when d0=1, calculating y=y×a (mod n) is performed. Then, outputting y=ad (mod n) is performed. In the first step, although an attacker inputs data including a minus value such as a=−1 and a=s, −s, etc., only plus values can be constantly generated in multiplication and squaring. Therefore, the method makes it hard to estimate a secret key using power analyzing attacks such as the SPA and the DPA, thereby realizing an encryption processor having high tamper-resistance.

摘要翻译： 基于用于从u位指数d =（du-1，...，d0）2执行指数余数计算y = ad（mod n）的加密方法，输入数据a和模n， '= a2（mod n）被首先执行。 接下来，对f =（du-1，du-2，...，d1）2进行y =（a'）f（mod n）的计算。 然后，当d0 = 1时，执​​行y = y×a（mod n）的计算。 然后，输出y = ad（mod n）。 在第一步中，尽管攻击者输入包括诸如a = -1和a = s，-s等的负值的数据，但是只能在乘法和平方中产生加值。 因此，该方法难以使用诸如SPA和DPA的功率分析攻击来估计秘密密钥，从而实现具有高抗篡改性的加密处理器。

公开(公告)号：US20100278340A1

公开(公告)日：2010-11-04

申请号：US12834252

申请日：2010-07-12

申请人： Jun YAJIMA ,  Dai YAMAMOTO ,  Kouichi ITOH

发明人： Jun YAJIMA ,  Dai YAMAMOTO ,  Kouichi ITOH

IPC分类号： H04K1/00

CPC分类号： H04L9/0625 ,  H04L2209/122 ,  H04L2209/24 ,  H04L2209/805

摘要： When processing a data conversion function of a MISTY structure, such as the FO function of MISTY1, the logical calculation result t3 of the exclusive OR 614 of the process result of the FI function 602 of the MISTY structure in the second stage and a logical calculation result t1 of an exclusive OR 612 of the MISTY structure in the first stage is not stored in a register. The logical calculation result t3 and the logical calculation result of respective exclusive OR 642 and 643 are subject to a direct exclusive OR with the respective exclusive OR 642 and 643.

摘要翻译： 当处理诸如MISTY1的FO功能的MISTY结构的数据转换功能时，第二级的MISTY结构的FI功能602的处理结果的异或614的逻辑计算结果t3和逻辑计算 第一级的MISTY结构的异或612的结果t1不存储在寄存器中。 逻辑运算结果t3和各异或642和643的逻辑计算结果与各自的异或642和643进行直接异或运算。

公开(公告)号：US07792893B2

公开(公告)日：2010-09-07

申请号：US11230592

申请日：2005-09-21

申请人： Kouichi Itoh ,  Masahiko Takenaka ,  Naoya Torii

发明人： Kouichi Itoh ,  Masahiko Takenaka ,  Naoya Torii

IPC分类号： G06F7/38 ,  G06F7/00

CPC分类号： G06F7/728

摘要： A method for calculating a conversion parameter of the Montgomery modular multiplication to improve the efficiency of software installation, comprising a first step for calculating H0=2v×R (mod n) (where v is an integer, v≧1, and (m×k)/v is an integer), a second step for calculating Hp=2v×2^p×R (mod n) from H0=2v×R (mod n) by repeating Hi=REDC(Hi−1, Hi−1)n with respect to i=1, 2, . . . , p (where p represents an integer satisfying the condition 2p≧(m×k)/v>2p−1, REDC represents the Montgomery modular multiplication REDC(a, b)n=a×b×R−1 (mod n), and x^i represents exponential computation xi); and a third step for calculating Hp=R2 (mod n) by calculating Hp=REDC(Hp, g)n with respect to Hp obtained in the second step when 2p>(m×k)/v (where g=2k×E(p,m,k), E(p, m, k)=2×m−(v×2p)/k) and finally outputting Hp as R2 (mod n).

摘要翻译： 一种用于计算蒙哥马利乘积的转换参数以提高软件安装效率的方法，包括计算H0 = 2v×R（mod n）的第一步骤（其中v是整数，v≥1，（m× k）/ v是整数），通过重复Hi = REDC（Hi-1，Hi-1）从H0 = 2v×R（mod n）计算Hp = 2v×2 ^ p×R（mod n） ）n相对于i = 1,2。 。 。 ，p（其中p表示满足条件2p≥（m×k）/ v> 2p-1的整数，REDC表示蒙哥马利模乘REDC（a，b）n = a×b×R-1（mod n） ，x ^ i表示指数计算xi）; 以及第三步骤，当2p>（m×k）/ v（其中g = 2k×E）时，通过计算相对于在第二步骤中获得的Hp的Hp = REDC（Hp，g）n来计算Hp = R2（mod n） （p，m，k），E（p，m，k）= 2×m-（v×2p）/ k），最后输出Hp为R2（mod n）。

公开(公告)号：US20090170178A1

公开(公告)日：2009-07-02

申请号：US10553601

申请日：2004-04-22

申请人： Miwako Ozaki ,  Kouichi Itoh

发明人： Miwako Ozaki ,  Kouichi Itoh

IPC分类号： C12N13/00 ,  C12M1/42

CPC分类号： C12M35/02 ,  C12M23/10 ,  C12N13/00

摘要： It is an object of the present invention to provide an electrical stimulating device for efficiently providing direct electrical stimulation to a large number of nerve cells in vitro without causing any injuries to such cells. The present invention provides a cell stimulating device which comprises: a first electrode serving as a positive or negative electrode that extends from one side of a culture vessel that is used for accommodating cultured cells to a point at which the first electrode is not in contact with the cultured cells or is in contact with the surfaces of the cultured cells; and a second electrode serving as a negative or positive electrode that extends from the other side of the culture vessel to a point at which the second electrode is not in contact with the cultured cells or is in contact with the surfaces of the cultured cells, wherein an electric field for stimulating cells is formed via the first electrode and the second electrode.

摘要翻译： 本发明的目的是提供一种电刺激装置，用于在体外有效地向大量神经细胞提供直接电刺激，而不会对这种细胞造成任何损伤。 本发明提供一种细胞刺激装置，其特征在于，包括：第一电极，其作为正极或负极，从用于容纳培养细胞的培养容器的一侧延伸到第一电极不接触的点 培养的细胞或与培养细胞的表面接触; 以及用作负极或正极的第二电极，其从培养容器的另一侧延伸到第二电极不与培养细胞接触的点或与培养细胞的表面接触，其中 经由第一电极和第二电极形成用于刺激细胞的电场。

公开(公告)号：US20080181395A1

公开(公告)日：2008-07-31

申请号：US11948447

申请日：2007-11-30

申请人： Souichi OKADA ,  Kouichi ITOH

发明人： Souichi OKADA ,  Kouichi ITOH

IPC分类号： H04L9/28

CPC分类号： H04L9/0631 ,  H04L2209/122

摘要： In a cryptographic operation apparatus, the result of an encryption process, or decryption process, is obtained by disposing two operational circuits in parallel, each comprising four multiplying devices and an exclusive-OR device, and by processing an input data string in two cycles; or by processing an input data string by a single operational circuit in four cycles.

摘要翻译： 在加密操作装置中，通过并行设置两个运算电路，每个包括四个乘法装置和异或装置，并且通过以两个周期处理输入数据串，获得加密处理或解密处理的结果。 或通过在四个周期内由单个操作电路处理输入数据串。

公开(公告)号：US20060093137A1

公开(公告)日：2006-05-04

申请号：US11311590

申请日：2005-12-16

申请人： Tetsuya Izu ,  Kouichi Itoh ,  Masahiko Takenaka ,  Naoya Torii

发明人： Tetsuya Izu ,  Kouichi Itoh ,  Masahiko Takenaka ,  Naoya Torii

IPC分类号： H04L9/30

CPC分类号： G06F7/725 ,  G06F2207/7223 ,  G06F2207/7228 ,  H04L9/003 ,  H04L9/3066 ,  H04L2209/08

摘要： An elliptic curve cryptosystem apparatus performing an elliptic curve cryptosystem process has a coordinate transforming unit for transforming coordinates (X:Y:Z) on a point P on an elliptic curve over a finite field GF(pˆm) to coordinates (r1×(X−s1):r2×(Y−s2):r3×(Z−s3)) (where, p is a prime number, m is an integer not less than 1, r1, r2 and r3 are integers not less than 1 and not larger than (p−1), s1, s2 and s3 are integer not less than 0 and not larger than (p−1), and a code “ˆ” represents power), and a scalar multiplication operating unit for performing scalar multiplication on the point on the elliptic curve transformed by the coordinate transforming unit, wherein at least one of the parameters s1, s2 and s3 has a value other than 0. The apparatus can perform the scalar multiplication in the elliptic curve cryptosystem, with resistance to side channel attacks.

摘要翻译： 执行椭圆曲线密码系统处理的椭圆曲线密码系统装置具有坐标变换单元，用于将有限域GF（pm）上的椭圆曲线上的点P上的坐标（X：Y：Z）变换为坐标（r1x（X-s1 ）：r2x（Y-s2）：r3x（Z-s3））（其中，p是质数，m是不小于1的整数，r1，r2和r3是不小于1且不大于 p-1），s1，s2和s3是不小于0且不大于（p-1）的整数，代码“”表示功率），以及标量乘法运算单元，用于对该点上的点进行标量乘法 由坐标变换单元变换的椭圆曲线，其中，参数s1，s2和s3中的至少一个具有不同于0的值。该装置可以执行椭圆曲线密码系统中具有抗侧信道攻击的标量乘法。

公开(公告)号：US20050152541A1

公开(公告)日：2005-07-14

申请号：US11045111

申请日：2005-01-31

申请人： Masahiko Takenaka ,  Tetsuya Izu ,  Kouichi Itoh ,  Naoya Torii

发明人： Masahiko Takenaka ,  Tetsuya Izu ,  Kouichi Itoh ,  Naoya Torii

IPC分类号： G06F7/72 ,  G09C1/00 ,  H04K1/00 ,  H04L9/30

CPC分类号： G06F7/725 ,  G06F2207/7223

摘要： An encryption device (FIG. 15) performs elliptic curve encryption using a secret key. The encryption device includes: operation means (ECDBL, ECADD) for performing scalar multiplication of a point on an elliptic curve; storage (T[0]-T[2]) having a plurality of data storing areas; and means (SEL) for determining, in accordance with a bit sequence of a given value (d) and with a random value (RNG), an address of one of the plurality of data storage areas that is to be coupled to the operation means for each scalar multiplication.

摘要翻译： 使用秘密密钥进行加密装置（图15