公开(公告)号：US4740827A

公开(公告)日：1988-04-26

申请号：US913383

申请日：1986-09-30

申请人： Youichiro Niitsu ,  Shinji Taguchi ,  Kenji Shibata ,  Kouichi Kanzaki

发明人： Youichiro Niitsu ,  Shinji Taguchi ,  Kenji Shibata ,  Kouichi Kanzaki

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L27/02 ,  H01L27/12 ,  H01L29/06

CPC分类号： H01L21/823878 ,  H01L21/7621 ,  H01L27/0921

摘要： In the CMOS semiconductor device having an epitaxial layer, a trench with an appropriate depth is formed in the vicinity of a boundary between a range in which a MOS transistor is formed and a well range in which another MOS transistor is formed; the inner wall surface of the trench is covered with a thermal oxide film; and the trench is buried with a semiconductor substance, so that two CMOS transistors can be electrically isolated by the trench to increase the latch-up holding voltage beyond a supply voltage (e.g. 5 v). Therefore, the latch-up proof resistance can be increased to protect the device from noise which otherwise would break the device. Further, the trench depth is shallower than the low impurity atom concentration layer (epitaxial layer) or 3 .mu.m but deeper than a value obtained by subtracting 2 .mu.m from the above thickness or 3 .mu.m.

摘要翻译： 在具有外延层的CMOS半导体器件中，在形成MOS晶体管的范围与形成另一MOS晶体管的阱范围之间的边界附近形成适当深度的沟槽; 沟槽的内壁表面被热氧化膜覆盖; 并且沟槽被半导体物质掩埋，使得两个CMOS晶体管可以通过沟槽电隔离以增加闩锁保持电压超过电源电压（例如5V）。 因此，可以提高防闩锁电阻以保护装置免受噪声，否则会破坏装置。 此外，沟槽深度比低杂质原子浓度层（外延层）浅3μm，但比通过从上述厚度或3μm减去2μm获得的值更深。