公开(公告)号：US07675088B2

公开(公告)日：2010-03-09

申请号：US12256456

申请日：2008-10-22

Applicant: Jun-Yao Huang ,  Kuang-Cheng Fu ,  Jen-Chieh Lin ,  Chin-Lung Yeh

Inventor： Jun-Yao Huang ,  Kuang-Cheng Fu ,  Jen-Chieh Lin ,  Chin-Lung Yeh

IPC: H01L21/336

CPC classification number: G02F1/136213 ,  G02F1/1345 ,  G02F2201/50 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255

Abstract: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a number of scan lines and a number of source lines are disposed on the substrate and define a number of pixel regions. A number of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A number of patterned thin films are disposed on the storage capacitance lines and above the cross portion.

Abstract translation: 本文公开了薄膜晶体管阵列基板及其制造方法。 第一图案化金属层，绝缘层，图案层和第二图案化金属层依次形成在基板上。 然后，多个扫描线和多条源极线设置在基板上并限定多个像素区域。 多个存储电容线沿着扫描线和跨越像素区域延伸的方向设置在基板上，其中每个保持电容线基本上垂直于每个源极线并且形成交叉部分。 多个图案化薄膜被设置在保持电容线上并且在十字部分之上。

公开(公告)号：US20090061553A1

公开(公告)日：2009-03-05

申请号：US12256456

申请日：2008-10-22

Applicant: Jun-Yao Huang ,  Kuang-Cheng Fu ,  Jen-Chieh Lin ,  Chin-Lung Yeh

Inventor： Jun-Yao Huang ,  Kuang-Cheng Fu ,  Jen-Chieh Lin ,  Chin-Lung Yeh

IPC: H01L21/336

CPC classification number: G02F1/136213 ,  G02F1/1345 ,  G02F2201/50 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255

Abstract: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a number of scan lines and a number of source lines are disposed on the substrate and define a number of pixel regions. A number of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A number of patterned thin films are disposed on the storage capacitance lines and above the cross portion.

Abstract translation: 本文公开了薄膜晶体管阵列基板及其制造方法。 第一图案化金属层，绝缘层，图案层和第二图案化金属层依次形成在基板上。 然后，多个扫描线和多条源极线设置在基板上并限定多个像素区域。 多个存储电容线沿着扫描线和跨越像素区域延伸的方向设置在基板上，其中每个保持电容线基本上垂直于每个源极线并形成交叉部分。 多个图案化薄膜被设置在保持电容线上并且在十字部分之上。

公开(公告)号：US20080054264A1

公开(公告)日：2008-03-06

申请号：US11649238

申请日：2007-01-04

Applicant: Jun-Yao Huang ,  Kuang-Cheng Fu ,  Jen-Chieh Lin ,  Chin-Lung Yeh

Inventor： Jun-Yao Huang ,  Kuang-Cheng Fu ,  Jen-Chieh Lin ,  Chin-Lung Yeh

IPC: H01L29/04

CPC classification number: G02F1/136213 ,  G02F1/1345 ,  G02F2201/50 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255

Abstract: A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a plurality of scan lines and a plurality of source lines are disposed on the substrate and define a plurality of pixel regions. A plurality of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A plurality of patterned thin films are disposed on the storage capacitance lines and above the cross portion.

Abstract translation: 本文公开了薄膜晶体管阵列基板及其制造方法。 第一图案化金属层，绝缘层，图案层和第二图案化金属层依次形成在基板上。 然后，多个扫描线和多条源极线设置在基板上并限定多个像素区域。 多条存储电容线沿着扫描线和跨越像素区域延伸的方向设置在基板上，其中每个保持电容线基本上垂直于每个源极线并形成交叉部分。 多个图案化薄膜被设置在辅助电容线上并且在十字部分之上。