Abstract:
A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.
Abstract:
A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
Abstract:
The present invention relates to an interpolation method for enlarging an image, wherein the image is composed of plural scanning lines. Firstly, it selects four adjacent continuous pixels xk−1, xk, xk+1, and xk+2 which have the pixel values f(xk−1), f(xk), f(xk+1), and f(xk+2) respectively on each of the scanning lines; next, it determines three linear equations Lk−1, Lk, and Lk+1 according to every two adjacent pixel values f(xk−1) and f(xk), f(xk) and f(xk+1), and f(xk+1) and f(xk+2), respectively; then, it selects a pixel x to be interpolated between the pixel xk and the pixel xk+1; finally, it applies the pixel x to the three linear equations Lk−1, Lk, and Lk+1 to determine three candidate pixel values which are weighted and combined to obtain pixel value f(x) of the pixel x.
Abstract:
A force sensing device and a force sensing system are provided. The force sensing device comprises at least one magnetic material layer and a force sensing layer which can move with respect to each other. The force sensing layer comprises two sensing elements. The first sensing element, disposed along a first axis of the magnetic material layer, generates a sensing signal varying with a first lateral force applied on the force sensing device. The first lateral force enables the first sensing element to move relatively with respect to the magnetic material layer along the first axis. The second sensing element, disposed along a second axis of the magnetic material layer, generates a sensing signal varying with a second lateral force applied on the force sensing device. The second lateral force enables the second sensing element to move relatively with respect to the magnetic material layer along the second axis.
Abstract:
A cleaning method for a wafer is provided. First, a first cleaning process is performed wherein the first cleaning process includes providing a cleaning solution having a first concentration. Next, a second cleaning process is performed, wherein the second cleaning process includes providing the cleaning solution having a second concentration. The second concentration is substantially greater than the first concentration. Next, a post-cleaning process is performed to provide dilute water.
Abstract:
A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
Abstract:
A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.
Abstract:
A thin film transistor array substrate and the manufacturing method thereof are disclosed herein. A first patterned metal layer, an insulating layer, a patterned layer, and a second patterned metal layer are sequentially formed on a substrate. Then, a number of scan lines and a number of source lines are disposed on the substrate and define a number of pixel regions. A number of the storage capacitance lines are disposed on the substrate in a direction extending along the scan lines and across the pixel regions, wherein each of the storage capacitance lines is essentially perpendicular to each of the source lines and to form a cross portion. A number of patterned thin films are disposed on the storage capacitance lines and above the cross portion.
Abstract:
A polyurethane composite is disclosed comprising rigid polyurethane and foamed thereupon a flexible integral skin (surface pore closed) polyurethane foam, wherein the rigid polyurethane having a density range of 600 kg/m3 to 1200 kg/m3, a Shore A hardness range of 90 to 99, a Shore D hardness range of 40 to 80, a tensile strength range of 10 MPa to 60 MPa, a flexural strength range of 20 MPa to 60 Mpa, a elastic flexural modulus range of 800 MPa to 2500 Mpa, an elongation rate at break of 10-100% and an elongation at break of 25-150%; wherein the flexible integral skin (surface pore closed) polyurethane foam having a density range of 60 kg/m3 to 200 kg/m3, a tensile strength of 60 kPa to 250 kPa, an elongation at break of 70-180%, a tearing strength of 130-220 N/m, a resilience of falling ball of 40-70%, IFD25% of 200-600 N and IFD65% of 600-1800 N.
Abstract translation:公开了一种聚氨酯复合材料,其包含刚性聚氨酯并在其上发泡柔性整体表面(表面孔封闭)聚氨酯泡沫,其中密度范围为600kg / m 3至1200kg / 肖氏A硬度范围为90至99,肖氏D硬度范围为40至80,拉伸强度范围为10MPa至60MPa,弯曲强度范围为20MPa至60Mpa, 弹性挠曲模量范围为800MPa〜2500Mpa,断裂伸长率为10〜100%,断裂伸长率为25〜150%。 其中所述柔性整体表皮(表面孔封闭)聚氨酯泡沫的密度范围为60kg / m 3至200kg / m 3,拉伸强度为60kPa至 250kPa,断裂伸长率为70-180%,撕裂强度为130-220N / m,回弹力为40-70%,IFD25%为200-600N,IFD65%为600-1800N 。
Abstract:
An immunoassay cartridge for sensing at least one analyte in a biological sample is disclosed. The immunoassay cartridge comprises a supporting plate, a reaction cavity made within the supporting plate and having at least one analyte-binding molecule immobilized therein, a sample receiving end connected to the reaction cavity to allow the biological sample to flow into the reaction cavity for forming at least one complex of the analyte and the analyte-binding molecule, a first package containing a recognizing molecule, a first channel communicating the first package and the reaction cavity to allow the recognizing molecule to flow into the reaction cavity for forming a first product of the complex and the complex-binding molecule, a second package containing a buffer solution and a second channel communicating the second package and the reaction cavity to allow the buffer solution to flow into the reaction cavity.