公开(公告)号：US20160259878A1

公开(公告)日：2016-09-08

申请号：US14635827

申请日：2015-03-02

申请人： Vijay Bhargava ,  Naveen Kumar ,  Kushagra Khorwal

发明人： Vijay Bhargava ,  Naveen Kumar ,  Kushagra Khorwal

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5031 ,  G06F2217/62

摘要： A method for achieving clock timing closure in an integrated circuit (IC) design includes designing an IC using one or more component cells selected from a cell library to produce the design. A timing analysis of the design is performed to determine if timing constraints are satisfied. When a given time constraint is not satisfied, a component cell selected from the cell library is replaced with a replacement cell that has the same function and the same footprint as the replaced component cell, but has a different timing characteristic based on the phase relationship of the signal being capacitively coupled to enhance the likelihood of meeting the given time constraint. The timing analysis is repeated with the replacement cell. The process of replacing component cells and performing timing analysis may be iterative.

摘要翻译： 用于在集成电路（IC）设计中实现时钟定时闭合的方法包括使用从单元库选择的一个或多个组件单元来设计IC以产生设计。 执行设计的定时分析以确定是否满足时序约束。 当不满足给定的时间约束时，从具有与被替代的分量单元相同的功能和相同的占空比的替换单元替换从单元库中选择的分量单元，但是具有基于相位关系的不同的定时特性 信号被电容耦合以增强满足给定时间约束的可能性。 用替换单元重复时序分析。 更换组件单元和执行时序分析的过程可能是迭代的。

公开(公告)号：US09003351B1

公开(公告)日：2015-04-07

申请号：US14150731

申请日：2014-01-08

申请人： Chetan Verma ,  Kushagra Khorwal ,  Amit Roy ,  Rounak Roy ,  Vijay Tayal

发明人： Chetan Verma ,  Kushagra Khorwal ,  Amit Roy ,  Rounak Roy ,  Vijay Tayal

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5068 ,  G06F2217/78

摘要： A method and system for reducing power consumption of an integrated circuit with an EDA tool by analyzing and modifying a layout design having a plurality of nets across multiple metal layers. The method includes identifying long nets in the layout design, determining an interconnect capacitance of each of the long nets, determining a net level switching activity of each of the long nets, generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, modifying a metal spacing of the long nets listed in the high power impact list.

摘要翻译： 一种通过分析和修改跨越多个金属层具有多个网络的布局设计来减少具有EDA工具的集成电路的功耗的方法和系统。 该方法包括在布局设计中识别长网，确定每个长网的互连电容，确定每个长网的净电平切换活动，使用互连电容产生高功率冲击列表，以及切换活动 每个长网，修改高功率影响列表中列出的长网的金属间距。

公开(公告)号：US09576101B2

公开(公告)日：2017-02-21

申请号：US14635827

申请日：2015-03-02

申请人： Vijay Bhargava ,  Naveen Kumar ,  Kushagra Khorwal

发明人： Vijay Bhargava ,  Naveen Kumar ,  Kushagra Khorwal

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5031 ,  G06F2217/62

摘要： A method for achieving clock timing closure in an integrated circuit (IC) design includes designing an IC using one or more component cells selected from a cell library to produce the design. A timing analysis of the design is performed to determine if timing constraints are satisfied. When a given time constraint is not satisfied, a component cell selected from the cell library is replaced with a replacement cell that has the same function and the same footprint as the replaced component cell, but has a different timing characteristic based on the phase relationship of the signal being capacitively coupled to enhance the likelihood of meeting the given time constraint. The timing analysis is repeated with the replacement cell. The process of replacing component cells and performing timing analysis may be iterative.

摘要翻译： 用于在集成电路（IC）设计中实现时钟定时闭合的方法包括使用从单元库选择的一个或多个组件单元来设计IC以产生设计。 执行设计的定时分析以确定是否满足时序约束。 当不满足给定的时间约束时，从具有与被替代的分量单元相同的功能和相同的占空比的替换单元替换从单元库中选择的分量单元，但是具有基于相位关系的不同的定时特性 信号被电容耦合以增强满足给定时间约束的可能性。 用替换单元重复时序分析。 更换组件单元和执行时序分析的过程可能是迭代的。