公开(公告)号：US07292430B2

公开(公告)日：2007-11-06

申请号：US11272877

申请日：2005-11-15

申请人： Byoung Hwa Lee ,  Chang Hoon Shim ,  Kyong Nam Hwang ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

发明人： Byoung Hwa Lee ,  Chang Hoon Shim ,  Kyong Nam Hwang ,  Dong Seok Park ,  Sang Soo Park ,  Min Cheol Park

IPC分类号： H01G4/228

CPC分类号： H01G4/232 ,  H01G4/30

摘要： A multi-layer chip capacitor includes a capacitor body; first and second internal electrodes alternately arranged therein and separated by dielectric layers, each of the internal electrodes having at least one opening formed at one or more sides thereof; first and second conductive vias passing through the openings and electrically connected to the first and second internal electrodes, respectively; first and second terminal electrodes of opposite polarities formed on one or more side faces of the capacitor body; and first and second lowermost electrode patterns being coplanar, each pattern including a via contact portion and a lead portion extending therefrom. The first and second lowermost electrode patterns are connected to the first and second terminal electrodes, respectively, through the respective lead portions of the lowermost patterns.

摘要翻译： 多层片式电容器包括电容器体; 第一和第二内部电极交替地布置在其中并由电介质层分离，每个内部电极具有形成在其一侧或多侧的至少一个开口; 第一和第二导电通孔分别穿过开口并电连接到第一和第二内部电极; 形成在电容器主体的一个或多个侧面上的相反极性的第一和第二端子电极; 并且第一和第二最低电极图案是共面的，每个图案包括通孔接触部分和从其延伸的引线部分。 第一和第二最下面的电极图案分别通过最下面图案的相应引线部分连接到第一和第二端子电极。