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1.发明授权Embedded multilayer chip capacitor and printed circuit board having the same 有权嵌入式多层片式电容器和具有相同功能的印刷电路板公开(公告)号：US07499258B2
公开(公告)日：2009-03-03
申请号：US11319722
申请日：2005-12-29
申请人： Chang Hoon Shim , Jin Yong An , Suk Hyeon Cho , Sung Hyung Kang
发明人： Chang Hoon Shim , Jin Yong An , Suk Hyeon Cho , Sung Hyung Kang
CPC分类号： H01G2/06 , H01G4/232 , H01G4/30 , H01L2924/0002 , H05K1/0231 , H05K1/185 , H05K2201/10643 , H01L2924/00
摘要： The invention provides an embedded multilayer chip capacitor, and a printed circuit board having the same. The embedded multilayer chip capacitor has a capacitor body having a plurality of dielectric layers stacked one on another; a plurality of first and second internal electrodes formed inside the capacitor body, separated by the dielectric layers; and first and second vias extended vertically inside the capacitor body. The first via is connected to the first internal electrodes and the second via is connected to the second internal electrodes. The first via is led to a bottom of the capacitor body and the second via is led to a top of the capacitor body.
摘要翻译： 本发明提供一种嵌入式多层片状电容器及具有该电容器的印刷电路板。 嵌入式多层片状电容器具有电容器主体，该电容器本体具有彼此层叠的多个电介质层; 多个第一和第二内部电极，形成在电容器本体内部，被电介质层分隔开; 并且第一和第二通孔在电容器体内垂直延伸。 第一通孔连接到第一内部电极，第二通孔连接到第二内部电极。 第一通孔被引导到电容器主体的底部，第二通孔被引导到电容器主体的顶部。
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公开(公告)号：US07292430B2
公开(公告)日：2007-11-06
申请号：US11272877
申请日：2005-11-15
申请人： Byoung Hwa Lee , Chang Hoon Shim , Kyong Nam Hwang , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Chang Hoon Shim , Kyong Nam Hwang , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
摘要： A multi-layer chip capacitor includes a capacitor body; first and second internal electrodes alternately arranged therein and separated by dielectric layers, each of the internal electrodes having at least one opening formed at one or more sides thereof; first and second conductive vias passing through the openings and electrically connected to the first and second internal electrodes, respectively; first and second terminal electrodes of opposite polarities formed on one or more side faces of the capacitor body; and first and second lowermost electrode patterns being coplanar, each pattern including a via contact portion and a lead portion extending therefrom. The first and second lowermost electrode patterns are connected to the first and second terminal electrodes, respectively, through the respective lead portions of the lowermost patterns.
摘要翻译： 多层片式电容器包括电容器体; 第一和第二内部电极交替地布置在其中并由电介质层分离，每个内部电极具有形成在其一侧或多侧的至少一个开口; 第一和第二导电通孔分别穿过开口并电连接到第一和第二内部电极; 形成在电容器主体的一个或多个侧面上的相反极性的第一和第二端子电极; 并且第一和第二最低电极图案是共面的，每个图案包括通孔接触部分和从其延伸的引线部分。 第一和第二最下面的电极图案分别通过最下面图案的相应引线部分连接到第一和第二端子电极。
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公开(公告)号：US07035079B1
公开(公告)日：2006-04-25
申请号：US11247404
申请日：2005-10-11
申请人： Sang Soo Park , Dong Seok Park , Byoung Hwa Lee , Min Cheol Park , Hyun Ju Yi , Min Kyoung Kwon , Hae Suk Chung , Chang Hoon Shim , Seung Heon Han
发明人： Sang Soo Park , Dong Seok Park , Byoung Hwa Lee , Min Cheol Park , Hyun Ju Yi , Min Kyoung Kwon , Hae Suk Chung , Chang Hoon Shim , Seung Heon Han
摘要： The present invention provides an MLCC and an MLCC array. The MLCC has desirably low ESL properties by forming the first and second internal electrodes to be spaced apart from each other on the same dielectric layer while overlapping with other first and second internal electrodes on the neighboring dielectric layers, and connecting the first and second internal electrodes to the external terminals provided on the top surface or the bottom surface of the capacitor body through conductive via holes formed in the capacitor body in a stacking direction of the capacitor body.
摘要翻译： 本发明提供了MLCC和MLCC阵列。 通过在相同的电介质层上形成第一和第二内部电极彼此间隔开，同时与相邻电介质层上的其它第一和第二内部电极重叠，并且连接第一和第二内部电极 通过形成在电容器主体中的电容器本体的堆叠方向上的导电通孔，连接到设置在电容器主体的顶表面或底表面上的外部端子。
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公开(公告)号：US07262952B2
公开(公告)日：2007-08-28
申请号：US11453880
申请日：2006-06-16
申请人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
IPC分类号： H01G4/228
摘要： The invention provides a multilayer chip capacitor reduced in ESL. A capacitor body has a plurality of dielectric layers stacked in a thickness direction. A plurality of first and second internal electrodes are separated from one another by the dielectric layers within the capacitor body. Each of the first internal electrodes opposes each of the second internal electrodes. Each of the first and second internal electrodes includes at least two leads extending toward any side of the capacitor body. Also, a plurality of external electrodes are formed on an outer surface of the capacitor body and connected to the internal electrodes via the leads. Further, vertically adjacent ones of the leads having the same polarity extend in different directions at a predetermined angle. The leads of the first and second internal electrodes are disposed adjacent to and alternate with those of the second internal electrodes.
摘要翻译： 本发明提供了一种减少ESL的多层片式电容器。 电容器本体具有沿厚度方向堆叠的多个电介质层。 多个第一和第二内部电极通过电容器体内的电介质层彼此分离。 每个第一内部电极与每个第二内部电极相对。 第一和第二内部电极中的每一个包括朝向电容器主体的任何一侧延伸的至少两个引线。 此外，多个外部电极形成在电容器主体的外表面上并经由引线连接到内部电极。 此外，具有相同极性的垂直相邻的引线以预定角度在不同方向上延伸。 第一和第二内部电极的引线设置成与第二内部电极的引线相邻并与其交替。
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5.发明授权Multilayered chip capacitor and printed circuit board having embedded multilayered chip capacitor 有权多层片式电容器和具有嵌入式多层片式电容器的印刷电路板公开(公告)号：US07230815B2
公开(公告)日：2007-06-12
申请号：US11288802
申请日：2005-11-29
申请人： Hee Soo Yoon , Chang Hoon Shim , Don Cheol Choi , Dong Hwan Lee
发明人： Hee Soo Yoon , Chang Hoon Shim , Don Cheol Choi , Dong Hwan Lee
摘要： A multilayered chip capacitor (MLCC) includes internal electrodes and external electrodes formed to be perpendicular to the internal electrodes, whereby parasitic capacitance is reduced, resulting in no parallel resonance frequency effects. In addition, the MLCC has a capacitor structure, which provides a first surface and a second surface formed in a stacking direction of the dielectric layers in the capacitor body as a top surface and a bottom surface. Hence, in the thin capacitors having the same size, the number of internal electrode layers is increased, thereby reducing the equivalent series resistant (ESR) and equivalent series inductance (ESL). Further, the printed circuit board (PCB) having an embedded MLCC is easily manufactured.
摘要翻译： 多层片状电容器（MLCC）包括形成为垂直于内部电极的内部电极和外部电极，由此寄生电容减小，导致没有并联谐振频率效应。 此外，MLCC具有电容器结构，其提供在电容器主体中的电介质层的堆叠方向上形成的第一表面和第二表面作为顶表面和底表面。 因此，在具有相同尺寸的薄电容器中，内部电极层的数量增加，从而降低等效串联电阻（ESR）和等效串联电感（ESL）。 此外，具有嵌入式MLCC的印刷电路板（PCB）容易制造。
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公开(公告)号：US07149072B2
公开(公告)日：2006-12-12
申请号：US11264486
申请日：2005-11-01
申请人： Byoung Hwa Lee , Hiroki Sato , Chang Hoon Shim , Sang Soo Park , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Hyun Ju Yi , Min Kyoung Kwon , Seung Heon Han
发明人： Byoung Hwa Lee , Hiroki Sato , Chang Hoon Shim , Sang Soo Park , Hae Suk Chung , Dong Seok Park , Min Cheol Park , Hyun Ju Yi , Min Kyoung Kwon , Seung Heon Han
CPC分类号： H05K1/0231 , H01G2/065 , H01G4/228 , H01G4/30 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16235 , H01L2924/00014 , H01L2924/15159 , H01L2924/19041 , H01L2924/19106 , H05K2201/10515 , H05K2201/1053 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.
摘要翻译： 这里公开了一种多层片状电容器阵列，其包括具有多个电介质层的电容器主体，多对第一和第二内部电极，形成在多个电介质层上，使得一对内部电极的一个电极面 一对内电极的另一个电极与介于其间的多个电介质层中的一个介于其间，至少一个第一外端子和多个第二外端子形成在第一外端子的顶表面和底表面的至少一个表面上 电容器本体，以及至少一个第一导电通孔和多个第二导电通孔，其形成在电容器主体的堆叠方向上，分别连接到第一外部端子和第二外部端子。
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公开(公告)号：US07092236B2
公开(公告)日：2006-08-15
申请号：US11068825
申请日：2005-03-02
申请人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
发明人： Byoung Hwa Lee , Chang Hoon Shim , Hae Suk Chung , Dong Seok Park , Sang Soo Park , Min Cheol Park
摘要： A multilayer chip capacitor, which reduces ESL generated due to current flowing through external electrodes and assures an improved mechanical strength. The multilayer chip capacitor includes an upper dummy layer and a lower dummy layer; a plurality of internal electrodes interposed between the upper and lower dummy layers; and external electrodes connected to the internal electrodes, wherein the thickness of the lower dummy layer is smaller than the thickness of the upper dummy layer.
摘要翻译： 一种多层片状电容器，其减少由于电流流过外部电极而产生的ESL，并确保改进的机械强度。 多层片状电容器包括上虚拟层和下虚拟层; 插入在上下虚拟层之间的多个内部电极; 以及连接到内部电极的外部电极，其中下部虚拟层的厚度小于上部虚拟层的厚度。
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公开(公告)号：US07046500B2
公开(公告)日：2006-05-16
申请号：US11068757
申请日：2005-03-02
申请人： Byoung Hwa Lee , Dong Seok Park , Min Cheol Park , Sang Soo Park , Chang Hoon Shim , Kyung Nam Hwang
发明人： Byoung Hwa Lee , Dong Seok Park , Min Cheol Park , Sang Soo Park , Chang Hoon Shim , Kyung Nam Hwang
摘要： A laminated ceramic capacitor includes a ceramic block formed by laminating a plurality of ceramic sheets, a plurality of external electrodes formed on outer surfaces of the ceramic block facing each other, and set as a positive terminal and a negative terminal, respectively, one or more first and second internal electrodes alternately arranged within the ceramic block such that electric currents flow in opposite directions in the internal electrodes, and a plurality of withdrawing patterns for connecting the first and second internal electrodes to the external electrodes, respectively.
摘要翻译： 层叠陶瓷电容器包括通过层叠多个陶瓷片而形成的陶瓷块，形成在彼此相对的陶瓷块的外表面上的多个外部电极，分别设置为正极端子和负极端子，一个或多个 第一和第二内部电极交替地布置在陶瓷块内，使得电流在内部电极中沿相反方向流动，以及多个用于将第一和第二内部电极连接到外部电极的抽出图案。
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公开(公告)号：US06940710B1
公开(公告)日：2005-09-06
申请号：US11029677
申请日：2005-01-06
摘要： A multilayered chip capacitor including a capacitor main body including a plurality of dielectric layers, which are laminated; at least one pair of first and second internal electrodes, each of which is formed on the corresponding one of the plural dielectric layers and includes at least one lead extended to one end of the corresponding dielectric layer; a plurality of external terminals formed on the outer surface of the capacitor main body, and respectively connected to the first and second internal electrodes through the leads; and at least one opened region, formed through the inner area of each of the first and second internal electrodes, for branching the flow of current so as to increase the offset quantity of parasitic inductances between the first and second internal electrodes.
摘要翻译： 一种多层片状电容器，其包括层叠有多个电介质层的电容器主体; 至少一对第一和第二内部电极，每个所述第一和第二内部电极形成在所述多个电介质层中的相应一个上，并且包括至少一个延伸到所述相应电介质层的一端的引线; 多个外部端子，形成在电容器主体的外表面上，分别通过引线连接到第一和第二内部电极; 以及通过第一和第二内部电极的每一个的内部区域形成的至少一个开放区域，用于分流电流，以增加第一和第二内部电极之间的寄生电感的偏移量。
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