公开(公告)号：US06574782B1

公开(公告)日：2003-06-03

申请号：US09713422

申请日：2000-11-15

申请人： L. William Dewey, III ,  Peter A. Habitz ,  Thomas G. Mitchell

发明人： L. William Dewey, III ,  Peter A. Habitz ,  Thomas G. Mitchell

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A structure and method for extracting parasitic capacitance from a multi-layer wiring structure that creates, for each wiring layer in a wiring structure, a wiring density map and measures a plurality of metal segments in a wiring layer to determine an area occupied by the metal segments. The invention calculates an up area capacitance component for each of the metal segments by multiplying the area occupied by the metal segments by a wiring density from the wiring density map of an overlying wiring layer over the metal segments and by a capacitance coefficient of the overlying wiring layer. To calculate the down area capacitance component for each of the metal segments, the invention multiplies the area occupied by the metal segments by a wiring density, from the wiring density map of an underlying wiring layer under the metal segments and by a capacitance coefficient of the underlying wiring layer. The invention combines the up area capacitance component and the down area capacitance component to form a vertical coupling capacitance component for each of the metal segments.

摘要翻译： 一种用于从多层布线结构中提取寄生电容的结构和方法，其对布线结构中的每个布线层产生布线密度图，并测量布线层中的多个金属片段，以确定金属占据的面积 细分。 本发明通过将金属片段占据的面积乘以金属片上覆盖布线层的布线密度图和布线密度乘以覆盖布线的电容系数来计算每个金属片段的面积电容分量 层。 为了计算每个金属段的下降面积电容分量，本发明根据金属段下面的布线层的布线密度图和金属段的电容系数将金属段所占的面积乘以布线密度 底层布线层。 本发明结合了上部区域电容分量和向下区域电容分量，以形成每个金属段的垂直耦合电容分量。

公开(公告)号：US06477686B1

公开(公告)日：2002-11-05

申请号：US09560577

申请日：2000-04-27

申请人： L. William Dewey, III ,  Peter A. Habitz

发明人： L. William Dewey, III ,  Peter A. Habitz

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A structure and method for performing a capacitance extraction on an integrated circuit, includes determining a parallel-plate capacitance between devices on different levels within the integrated circuit, adding extension shapes around each of the devices, reducing an area of overlapping extension shapes, multiplying a remaining area of the extension shapes by a constant to produce a fringe capacitance; and summing the parallel-plate capacitance and the fringe capacitance.

摘要翻译： 一种用于在集成电路上执行电容提取的结构和方法，包括：确定集成电路内不同级别的器件之间的平行板电容，在每个器件周围增加扩展形状，减少重叠扩展形状的面积，将 延伸形状的剩余面积为常数以产生边缘电容; 并且平行板电容和边缘电容相加。

公开(公告)号：US06473887B1

公开(公告)日：2002-10-29

申请号：US09560065

申请日：2000-04-27

申请人： L. William Dewey, III ,  Peter A. Habitz ,  Edward W. Seibert

发明人： L. William Dewey, III ,  Peter A. Habitz ,  Edward W. Seibert

IPC分类号： G06F945

CPC分类号： G06F17/5036

摘要： A method and structure for performing capacitance extraction during the design of an integrated circuit includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency factor based on the wiring density, calculating a lateral capacitance assuming virtual wires are present in the integrated circuit, and calculating a vertical capacitance based on the transparency factor.

摘要翻译： 在集成电路设计期间进行电容提取的方法和结构包括输入指定的布线密度和设计要求，根据设计要求确定线段的最小间距，根据布线密度计算透明度因子，计算出 在集成电路中存在假想虚线的横向电容，并且基于透明度因子计算垂直电容。

公开(公告)号：US06430729B1

公开(公告)日：2002-08-06

申请号：US09494975

申请日：2000-01-31

申请人： L. William Dewey ,  Peter A. Habitz ,  Judith H. McCullen ,  Edward W. Seibert

发明人： L. William Dewey ,  Peter A. Habitz ,  Judith H. McCullen ,  Edward W. Seibert

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method and structure for a method of determining characteristics of parasitic elements in an integrated circuit comprising, identifying manufacturing process parameters of devices in the integrated circuit, calculating a parasitic performance distribution for each of the devices based on the manufacturing process parameters, combining the parasitic performance distribution for each of the devices into a net parasitic value, and forming a parameterized model based on the net parasitic values.

摘要翻译： 一种用于确定集成电路中的寄生元件的特性的方法的方法和结构，包括：识别集成电路中的器件的制造工艺参数，基于制造工艺参数计算每个器件的寄生性能分布，组合寄生 每个器件的性能分布成为净寄生值，并且基于净寄生值形成参数化模型。

公开(公告)号：US06519752B1

公开(公告)日：2003-02-11

申请号：US09561096

申请日：2000-04-28

申请人： William C. Bakker ,  L. William Dewey, III ,  Peter A. Habitz ,  Judith H. McCullen ,  Edward W. Seibert ,  Michael J. Sullivan

发明人： William C. Bakker ,  L. William Dewey, III ,  Peter A. Habitz ,  Judith H. McCullen ,  Edward W. Seibert ,  Michael J. Sullivan

IPC分类号： G06F1750

CPC分类号： G06F17/5036

摘要： A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the fingers and the sub-fingers have similar characteristics, combining ones of the fingers and the sub-fingers that have similar characteristics into combined fingers, and extracting parasitic values from the fingers, the sub-fingers and the combined fingers.

摘要翻译： 一种用于对多指装置执行寄生提取的方法和结构，包括：建立装置的手指的最大处理宽度，将超过最大宽度的装置的手指分成子手指，确定手指中是否有手指 子手指具有类似的特征，将具有类似特征的手指和子手指组合成组合手指，并从手指，子手指和组合手指中提取寄生值。

公开(公告)号：US06460167B1

公开(公告)日：2002-10-01

申请号：US09559800

申请日：2000-04-27

申请人： L. William Dewey, III ,  Peter A. Habitz

发明人： L. William Dewey, III ,  Peter A. Habitz

IPC分类号： G06F1750

CPC分类号： G06F17/5081

摘要： A structure and method for evaluating an integrated circuit design includes adding a superseding layer of the integrated circuit design over a previous layer of the integrated circuit structure, identifying database pointers for regions and edges within the superseding layer and the previous layer, removing database pointers for regions of the previous layer overlapped by the superseding layer, classifying the superseding layer and the previous layer as the previous layer, and repeating the method until all layers of the integrated circuit are evaluated.

摘要翻译： 用于评估集成电路设计的结构和方法包括在集成电路结构的先前层上添加集成电路设计的替代层，识别替代层和先前层中的区域和边缘的数据库指针，去除数据库指针 上一层的区域与替代层重叠，将取代层和先前层分类为上一层，并重复该方法直到评估集成电路的所有层。