公开(公告)号：US20070109829A1

公开(公告)日：2007-05-17

申请号：US11272690

申请日：2005-11-15

申请人： Chi-Sheng Lin ,  Chun-Ming Huang ,  Lan-Da Van ,  Nien-Hsiang Chang ,  Chun-Pin Lin ,  Chih-Hsien Hsu ,  Chau-Chin Wang

发明人： Chi-Sheng Lin ,  Chun-Ming Huang ,  Lan-Da Van ,  Nien-Hsiang Chang ,  Chun-Pin Lin ,  Chih-Hsien Hsu ,  Chau-Chin Wang

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A dynamic time sequence control device and its method for a word matching circuit. The word matching circuit includes a first switch connected between an input voltage and a node to respond to a control signal generated by a pre-charging circuit so that within a pre-charging phase period a current is generated to flow through a capacitor to generate a charging voltage. The node is connected to multiple data memories and matching circuits so that the matching result can be outputted through the node. The dynamic time sequence control device includes a second switch connected between the first switch and the node. A third switch is connected between the data memory and matching circuit and a self time sequence controller has a threshold value to respond to the control signal and to conduct the second switch and turn off the third switch during the pre-charging phase period, meanwhile, it turns off the second switch and conducts the third switch when the charging voltage is detected to be larger than threshold value. The self time sequence controller detects the output voltage of the node and outputs the data matching result during a value-acquisition phase period.

摘要翻译： 一种动态时序控制装置及其字符匹配电路的方法。 字匹配电路包括连接在输入电压和节点之间的第一开关，以响应由预充电电路产生的控制信号，使得在预充电阶段期间内产生电流以流过电容器以产生 充电电压。 节点连接到多个数据存储器和匹配电路，以便可以通过节点输出匹配结果。 动态时序控制装置包括连接在第一开关和节点之间的第二开关。 第三开关连接在数据存储器和匹配电路之间，自适应时序控制器具有阈值以响应控制信号并导通第二开关并在预充电阶段期间关闭第三开关， 当检测到充电电压大于阈值时，它关闭第二开关并导通第三开关。 自适应时序控制器检测节点的输出电压，并在数据采集阶段期间输出数据匹配结果。

公开(公告)号：US07571414B2

公开(公告)日：2009-08-04

申请号：US11453103

申请日：2006-06-15

申请人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

发明人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/66

摘要： A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

摘要翻译： 通过将多个系统级芯片项目集成到一个使用系统芯片工作台的芯片上，因此微处理器，总线，嵌入式存储器，外设组件和输入/输出端口都集成在一起的多项目片上系统 因此，这些系统级芯片项目和每个片上系统的平均成本因此降低。 此外，本发明提出了一种多项目片上系统工作台的设计方法，使用户可以在每个设计流程层次上有效管理可用的数据和验证环境，从而简化设计过程流程 从而得出。

公开(公告)号：US20070294658A1

公开(公告)日：2007-12-20

申请号：US11453103

申请日：2006-06-15

申请人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

发明人： Chun-Ming Huang ,  Chih-Chyau Yang ,  Jing-Yang Jou ,  Kuen-Jong Lee ,  Lan-Da Van

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/66

摘要： A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip projects and the average cost of each system-on-chip is thus reduced. Moreover, this invention proposes a design method for multi-project system-on-chip bench, it let the user can effectively manage available data and verification environment in each design process flow hierarchy and in turn an easy-to-use design process flow is thus derived.

摘要翻译： 通过将多个系统级芯片项目集成到一个使用系统芯片工作台的芯片上，因此微处理器，总线，嵌入式存储器，外设组件和输入/输出端口都集成在一起的多项目片上系统 因此，这些系统级芯片项目和每个片上系统的平均成本因此降低。 此外，本发明提出了一种多项目片上系统工作台的设计方法，使用户可以在每个设计流程层次上有效管理可用的数据和验证环境，从而简化设计过程流程 从而得出。