公开(公告)号：US08959985B2

公开(公告)日：2015-02-24

申请号：US13547061

申请日：2012-07-12

Applicant: Chun-ming Huang ,  Chen-chia Chen ,  Chi-sheng Lin ,  Chien-ming Wu

Inventor： Chun-ming Huang ,  Chen-chia Chen ,  Chi-sheng Lin ,  Chien-ming Wu

IPC: G01N15/10

CPC classification number: G01N21/85 ,  G01N15/0272 ,  G01N2015/0065 ,  G01N2021/8571

Abstract: A microparticle detecting apparatus is disclosed and includes at least one detection unit, each of which includes: a first sieve having at least a first mesh, a separator stacked on one side of the first sieve and having a separator hole, and a second sieve stacked on one side of the separator and having several second meshes. The diameter of the second mesh is smaller than that of the first mesh, and the first and second meshes are misaligned with each other in a vertical direction of the first and second sieves. The detection unit further includes at least a sensor aligned with the first or second mesh for detecting microparticles trapping into the first mesh or passing through the second mesh. Therefore, the microparticle detecting apparatus is suitably used for detecting or counting any microparticles with different size, to effectively shorten the detection processes of sample fluids.

Abstract translation: 公开了一种微粒检测装置，包括至少一个检测单元，每个检测单元包括：具有至少第一筛网的第一筛网，堆叠在第一筛子的一侧上并具有分隔件孔的隔板，以及堆叠的第二筛 在分离器的一侧并具有多个第二网格。 第二网格的直径小于第一网格的直径，并且第一和第二网格在第一和第二筛网的垂直方向上彼此不对准。 检测单元还包括至少一个与第一或第二网格对准的传感器，用于检测捕获到第一网孔中的微粒或通过第二网孔。 因此，微粒检测装置适合用于检测或计数不同尺寸的微粒，以有效地缩短样品流体的检测过程。

公开(公告)号：US08911687B2

公开(公告)日：2014-12-16

申请号：US13547072

申请日：2012-07-12

Applicant: Chun-ming Huang ,  Chen-chia Chen ,  Chi-sheng Lin ,  Chien-ming Wu

Inventor： Chun-ming Huang ,  Chen-chia Chen ,  Chi-sheng Lin ,  Chien-ming Wu

IPC: B01D35/00 ,  B01D41/00 ,  B01D29/07

CPC classification number: B01L3/50255 ,  B01L2200/0668 ,  B01L2300/0681 ,  B01L2300/0819 ,  B01L2300/0893 ,  B01L2400/049 ,  G01N15/0272

Abstract: A miniature sieve apparatus is described and includes a first sieve, a separator and a second sieve from top to bottom. The first and second sieves are formed with at least one first mesh and a plurality of second meshes, respectively. The first and second meshes are misaligned with each other in a vertical direction of the first and second sieves. The miniature sieve apparatus is provided to separate or screen microparticles with different sizes, such as target cells, bio-medical particles, organic or inorganic microparticles. Additionally, the invention also provides a manufacturing method of the miniature sieve apparatus, and the same material is applied to manufacture the sieves and the separators. Thus, the problem caused by the residual thermal stress due to different material can be solved. Therefore, the cost of the miniature sieve apparatus can be lowered as the yield rate thereof is improved.

Abstract translation: 描述了一种微型筛装置，并且包括从顶部到底部的第一筛子，分离器和第二筛子。 第一和第二筛分别形成有至少一个第一网格和多个第二网格。 第一和第二网格在第一和第二筛的垂直方向上彼此不对准。 提供微型筛装置以分离或筛选不同尺寸的微粒，例如靶细胞，生物医学颗粒，有机或无机微粒。 此外，本发明还提供了一种微型筛装置的制造方法，并且将相同的材料应用于制造筛子和分离器。 因此，可以解决由于不同材料导致的残余热应力引起的问题。 因此，随着成品率的提高，微型筛装置的成本可以降低。

公开(公告)号：US08399303B1

公开(公告)日：2013-03-19

申请号：US13308604

申请日：2011-12-01

Applicant: Chun-Ming Huang ,  Chi-Sheng Lin ,  Chi-Shi Chen ,  Chien-Ming Wu

Inventor： Chun-Ming Huang ,  Chi-Sheng Lin ,  Chi-Shi Chen ,  Chien-Ming Wu

IPC: H01L21/44 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49861 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/81 ,  H01L2924/014

Abstract: The present invention provides a method for manufacturing a modularized integrated circuit (IC). The method includes the following steps: providing a base; and coupling an input/output module with the base. The base includes a lead-frame and a first package. The first package covers the lead-frame but exposes first contact points. The input/output module includes a first substrate, a plurality of first conducting columns, and a plurality of third contact points. A portion of each of the third contact points is electrically connected to a corresponding one of the first contact points. The method enhances the flexibility of IC design, and reduces the time and costs of developing new process techniques.

Abstract translation: 本发明提供了一种用于制造模块化集成电路（IC）的方法。 该方法包括以下步骤：提供基座; 并将输入/输出模块与基座耦合。 基座包括引线框架和第一封装。 第一个封装覆盖引线框架，但暴露了第一个接触点。 输入/输出模块包括第一基板，多个第一导电柱和多个第三接触点。 每个第三接触点的一部分电连接到相应的一个第一接触点。 该方法提高了IC设计的灵活性，并缩短了开发新工艺技术的时间和成本。

公开(公告)号：US08274794B2

公开(公告)日：2012-09-25

申请号：US12752345

申请日：2010-04-01

Applicant: Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

Inventor： Chun-Ming Huang ,  Chin-Long Wey ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chi-Shi Chen ,  Chi-Sheng Lin

IPC: H05K7/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K1/14 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/00

Abstract: A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements.

Abstract translation: 提供了通过堆叠多个芯片模块形成的三维SoC结构。 三维SoC结构包括至少两个垂直SoC模块和至少一个连接器模块，其中每个连接器模块电连接两个垂直SoC模块。 每个垂直SoC模块通过垂直堆叠至少两个芯片模块构成。 每个芯片模块包括模块电路板和至少一个预设元件。 在每个模块电路板中形成凹部，并设置有用于与相应的至少一个预设元件电连接的第一连接接口。 至少两个垂直SoC模块通过连接器模块连接，形成具有多种功能的三维SoC结构。 此外，形成在模块电路板中的凹部为预设元件提供有效的散热路径。

公开(公告)号：US20100330741A1

公开(公告)日：2010-12-30

申请号：US12570049

申请日：2009-09-30

Applicant: Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chin-Long Wey ,  Chi-Shi Chen ,  Chi-Sheng Lin

Inventor： Chun-Ming Huang ,  Chien-Ming Wu ,  Chih-Chyau Yang ,  Shih-Lun Chen ,  Chin-Long Wey ,  Chi-Shi Chen ,  Chi-Sheng Lin

IPC: H01L21/56

CPC classification number: H01L23/3128 ,  H01L23/38 ,  H01L23/467 ,  H01L25/105 ,  H01L25/16 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/19105 ,  H01L2924/00

Abstract: A fabrication method for a system-on-chip (SoC) module is provided. The fabrication method includes the steps of providing at least two SoC sub-modules and connecting the SoC sub-modules. The SoC sub-modules are electrically connected with each other by connection interfaces of the SoC sub-modules so as to form the SoC module. As the SoC sub-modules have been verified in advance, the time required for verifying the resulting SoC module can be significantly reduced. As for application-specific SoC modules, they are fabricated by connecting with application-specific SoC sub-modules via the appropriate connection interfaces. Thus, the time and costs for developing SoC modules can both be minimized.

Abstract translation: 提供了一种片上系统（SoC）模块的制造方法。 该制造方法包括提供至少两个SoC子模块并连接SoC子模块的步骤。 SoC子模块通过SoC子模块的连接接口彼此电连接，形成SoC模块。 由于SoC子模块已经被提前验证，所以可以显着地减少验证所得到的SoC模块所需的时间。 对于特定于应用的SoC模块，它们是通过与特定应用的SoC子模块通过适当的连接接口进行连接而制造的。 因此，开发SoC模块的时间和成本都可以最小化。

公开(公告)号：US07859313B2

公开(公告)日：2010-12-28

申请号：US12489624

申请日：2009-06-23

Applicant: Ting Hsu Chien ,  Chi Sheng Lin ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

Inventor： Ting Hsu Chien ,  Chi Sheng Lin ,  Chin-Long Wey ,  Chun-Ming Huang ,  Ying-Zong Juang

IPC: H03K5/19 ,  H03K5/22

CPC classification number: H03K5/19 ,  H03K5/1534 ,  H03L7/0891 ,  H03L7/10

Abstract: An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2π. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock.

Abstract translation: 边缘丢失检测器结构包括第一检测器，第一延迟单元，第一逻辑门，第二检测器，第二延迟单元和第二逻辑门。 在分别输入到边缘丢失检测器结构中之后，第一和第二检测器检测第一参考信号和第一时钟信号，然后分别由第一和第二逻辑门进行循环抑制，以产生 第二参考信号和呈现小于2＆pgr的相位差的第二时钟信号。 此外，边缘丢失检测器结构产生对应于循环抑制的出现次数的补偿电流。 因此，使用边缘丢失检测器结构的锁相环（PLL）可以避免周期滑移问题并实现锁相的快速采集。

公开(公告)号：US20100245703A1

公开(公告)日：2010-09-30

申请号：US12480696

申请日：2009-06-09

Applicant: Chi-Sheng Lin

Inventor： Chi-Sheng Lin

IPC: G02F1/13357

CPC classification number: G02F1/133308 ,  G02B6/0068 ,  G02B6/0083 ,  G02B6/009 ,  G02F1/133615 ,  G02F2001/133612

Abstract: A liquid crystal display (LCD) includes an LCD panel, a backlight module, and a circuit board. The backlight module disposed under the LCD panel includes a back plate, a light emitting diode (LED) light source, a protrusion, and a light guide plate. The LED light source disposed in the back plate includes a substrate and LEDs. The protrusion and the LEDs are disposed on the substrate, and the protrusion has first power contacts. The light guide plate is disposed between the back plate and the LCD panel and has a light entering surface. A light emitting surface of each of the LEDs faces the light entering surface. The circuit board disposed under the back plate is electrically connected to the LCD panel. The circuit board has a circuit layout and second power contacts, and the second power contacts contact the first power contacts correspondingly.

Abstract translation: 液晶显示器（LCD）包括LCD面板，背光模块和电路板。 布置在LCD面板下方的背光模块包括背板，发光二极管（LED）光源，突起和导光板。 设置在背板中的LED光源包括基板和LED。 突起和LED设置在基板上，并且突起具有第一电力接触。 导光板配置在背板与LCD面板之间，具有光入射面。 每个LED的发光表面面向光入射表面。 布置在背板下方的电路板电连接到LCD面板。 电路板具有电路布局和第二电源触点，并且第二电源触点相应地接触第一电源触点。

公开(公告)号：US07449962B2

公开(公告)日：2008-11-11

申请号：US11523637

申请日：2006-09-20

Applicant: Ting-Hsu Chien ,  Chi-Sheng Lin

Inventor： Ting-Hsu Chien ,  Chi-Sheng Lin

IPC: H03L7/085

CPC classification number: H03L7/085 ,  H03L7/0895

Abstract: A phase-controlled current source for phase-locked loop is provided. The phase-locked loop includes a voltage-controlled oscillator to associate a charging path or discharging path in order to generate an output signal and the output signal is further sensed so as to generate a loop signal. The phase-controlled current source includes a status memory receiving the loop signal and the reference signal so as to output an energy-triggering/energy-removing signal; and a controllable current source, under the control by energy-triggering/energy-removing signal so as to decide whether a charging and discharging action should be performed, wherein after the charging action or discharging action is decided, the charging path or the discharging path is generated through the reference signal and the loop signal.

Abstract translation: 提供了一个用于锁相环的相控电流源。 锁相环包括压控振荡器，以将充电路径或放电路径相关联，以便产生输出信号，并且进一步感测输出信号以产生回路信号。 相控电流源包括接收回路信号和参考信号的状态存储器，以输出能量触发/能量消除信号; 以及可控电流源，在能量触发/能量去除信号的控制下，以决定是否应执行充电和放电动作，其中在确定充电动作或放电动作之后，充电路径或放电路径 通过参考信号和环路信号产生。

公开(公告)号：US20070109829A1

公开(公告)日：2007-05-17

申请号：US11272690

申请日：2005-11-15

Applicant: Chi-Sheng Lin ,  Chun-Ming Huang ,  Lan-Da Van ,  Nien-Hsiang Chang ,  Chun-Pin Lin ,  Chih-Hsien Hsu ,  Chau-Chin Wang

Inventor： Chi-Sheng Lin ,  Chun-Ming Huang ,  Lan-Da Van ,  Nien-Hsiang Chang ,  Chun-Pin Lin ,  Chih-Hsien Hsu ,  Chau-Chin Wang

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A dynamic time sequence control device and its method for a word matching circuit. The word matching circuit includes a first switch connected between an input voltage and a node to respond to a control signal generated by a pre-charging circuit so that within a pre-charging phase period a current is generated to flow through a capacitor to generate a charging voltage. The node is connected to multiple data memories and matching circuits so that the matching result can be outputted through the node. The dynamic time sequence control device includes a second switch connected between the first switch and the node. A third switch is connected between the data memory and matching circuit and a self time sequence controller has a threshold value to respond to the control signal and to conduct the second switch and turn off the third switch during the pre-charging phase period, meanwhile, it turns off the second switch and conducts the third switch when the charging voltage is detected to be larger than threshold value. The self time sequence controller detects the output voltage of the node and outputs the data matching result during a value-acquisition phase period.

Abstract translation: 一种动态时序控制装置及其字符匹配电路的方法。 字匹配电路包括连接在输入电压和节点之间的第一开关，以响应由预充电电路产生的控制信号，使得在预充电阶段期间内产生电流以流过电容器以产生 充电电压。 节点连接到多个数据存储器和匹配电路，以便可以通过节点输出匹配结果。 动态时序控制装置包括连接在第一开关和节点之间的第二开关。 第三开关连接在数据存储器和匹配电路之间，自适应时序控制器具有阈值以响应控制信号并导通第二开关并在预充电阶段期间关闭第三开关， 当检测到充电电压大于阈值时，它关闭第二开关并导通第三开关。 自适应时序控制器检测节点的输出电压，并在数据采集阶段期间输出数据匹配结果。

公开(公告)号：US20130110465A1

公开(公告)日：2013-05-02

申请号：US13312219

申请日：2011-12-06

Applicant: Chun-Ming Huang ,  Chi-Sheng Lin ,  Chien-Ming Wu

Inventor： Chun-Ming Huang ,  Chi-Sheng Lin ,  Chien-Ming Wu

IPC: G06F17/40

CPC classification number: G01R31/2856 ,  G01R31/31707

Abstract: A chip structure having a history recording unit is provided. The chip structure includes a core circuit unit in addition to the history recording unit. The history recording unit includes a sensing unit, a record unit, and a deliver unit. The sensing unit detects the status of the core circuit unit and generates history information accordingly. The history information is saved into the record unit and can be further output by the deliver unit. Thus, the history information of the chip structure can be recorded and effectively used to eliminate the reliability problem of the chip structure.

Abstract translation: 提供具有历史记录单元的芯片结构。 除了历史记录单元之外，芯片结构还包括核心电路单元。 历史记录单元包括感测单元，记录单元和传送单元。 感测单元检测核心电路单元的状态并相应地生成历史信息。 历史信息被保存到记录单元中，并且可以由传送单元进一步输出。 因此，可以记录和有效地利用芯片结构的历史信息来消除芯片结构的可靠性问题。