Method and apparatus for thermal modeling and analysis of semiconductor chip designs
    1.
    发明授权
    Method and apparatus for thermal modeling and analysis of semiconductor chip designs 有权
    用于半导体芯片设计的热建模和分析的方法和装置

    公开(公告)号:US08082137B2

    公开(公告)日:2011-12-20

    申请号:US12137344

    申请日:2008-06-11

    IPC分类号: G06F17/50 G06F11/22

    摘要: A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.

    摘要翻译: 提供了半导体芯片设计的建模和热分析的方法和装置。 用于执行半导体芯片设计的热测试的新颖方法的一个实施例包括计算半导体芯片设计上的全芯片温度(例如,识别陡峭的热梯度),并根据几何多格网建模全芯片温度 技术。 几何多格网技术被定制以至少部分地基于设计的物理属性或几何形状来确定半导体芯片设计内的温度。

    Method and apparatus for thermal modeling and analysis of semiconductor chip designs
    2.
    发明授权
    Method and apparatus for thermal modeling and analysis of semiconductor chip designs 有权
    用于半导体芯片设计的热建模和分析的方法和装置

    公开(公告)号:US07401304B2

    公开(公告)日:2008-07-15

    申请号:US11180353

    申请日:2005-07-13

    IPC分类号: G06F17/50

    摘要: A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.

    摘要翻译: 提供了半导体芯片设计的建模和热分析的方法和装置。 用于执行半导体芯片设计的热测试的新颖方法的一个实施例包括计算半导体芯片设计上的全芯片温度(例如,识别陡峭的热梯度),并根据几何多格网建模全芯片温度 技术。 几何多格网技术被定制以至少部分地基于设计的物理属性或几何形状来确定半导体芯片设计内的温度。

    Method and apparatus for thermal modeling and analysis of semiconductor chip designs
    3.
    发明申请
    Method and apparatus for thermal modeling and analysis of semiconductor chip designs 有权
    用于半导体芯片设计的热建模和分析的方法和装置

    公开(公告)号:US20060031794A1

    公开(公告)日:2006-02-09

    申请号:US11180353

    申请日:2005-07-13

    IPC分类号: G06F17/50

    摘要: A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.

    摘要翻译: 提供了半导体芯片设计的建模和热分析的方法和装置。 用于执行半导体芯片设计的热测试的新颖方法的一个实施例包括计算半导体芯片设计上的全芯片温度(例如,识别陡峭的热梯度),并根据几何多格网建模全芯片温度 技术。 几何多格网技术被定制以至少部分地基于设计的物理属性或几何形状来确定半导体芯片设计内的温度。

    Programmable gate array based on configurable metal interconnect vias
    4.
    发明授权
    Programmable gate array based on configurable metal interconnect vias 有权
    基于可配置金属互连通孔的可编程门阵列

    公开(公告)号:US06633182B2

    公开(公告)日:2003-10-14

    申请号:US09947289

    申请日:2001-09-05

    IPC分类号: H03K738

    CPC分类号: H01L27/118 G06F17/5054

    摘要: A method is comprised of translating a bit stream defining the state of switches of an FPGA into a set of via geometries, or generating the set of via geometries directly from a physical design system. The via geometries are used to produce at least one via mask. The via mask is then used in a manufacturing process to customize an array of fixed and/or programmable logic blocks.

    摘要翻译: 一种方法包括将定义FPGA的开关状态的位流转换成一组通孔几何形状,或者直接从物理设计系统生成该组通孔几何形状。 通孔几何形状用于产生至少一个通孔掩模。 然后,在制造过程中使用通孔掩模来定制固定和/或可编程逻辑块阵列。

    METHOD AND APPARATUS FOR THERMAL MODELING AND ANALYSIS OF SEMICONDUCTOR CHIP DESIGNS
    5.
    发明申请
    METHOD AND APPARATUS FOR THERMAL MODELING AND ANALYSIS OF SEMICONDUCTOR CHIP DESIGNS 有权
    用于热模拟和半导体芯片设计分析的方法和装置

    公开(公告)号:US20080243461A1

    公开(公告)日:2008-10-02

    申请号:US12137344

    申请日:2008-06-11

    IPC分类号: G06F17/50

    摘要: A method and apparatus for modeling and thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for performing thermal testing of a semiconductor chip design includes calculating full-chip temperatures over the semiconductor chip design (e.g., to identify steep thermal gradients) and modeling the full-chip temperatures in accordance with a geometric multi-grid technique. The geometric multi-grid technique is tailored to determine temperatures within the semiconductor chip design based at least in part on the physical attributes or geometry of the design.

    摘要翻译: 提供了半导体芯片设计的建模和热分析的方法和装置。 用于执行半导体芯片设计的热测试的新颖方法的一个实施例包括计算半导体芯片设计上的全芯片温度(例如,识别陡峭的热梯度),并根据几何多格网建模全芯片温度 技术。 几何多格网技术被定制以至少部分地基于设计的物理属性或几何形状来确定半导体芯片设计内的温度。

    Statistical optimization and design method for analog and digital circuits
    6.
    发明申请
    Statistical optimization and design method for analog and digital circuits 有权
    模拟和数字电路的统计优化和设计方法

    公开(公告)号:US20060095888A1

    公开(公告)日:2006-05-04

    申请号:US11245892

    申请日:2005-10-07

    申请人: Xin Li Larry Pileggi

    发明人: Xin Li Larry Pileggi

    IPC分类号: G06F17/10 G06F17/50

    CPC分类号: G06F17/5036 G06F2217/10

    摘要: A computer implemented method of performing projection based polynomial fitting. The method includes generating a plurality of sampling points as a function of variables. The method also includes forming a polynomial model template representative of the plurality of sampling points. According to embodiments of the present invention, the polynomial model template comprises at least one polynomial coefficient. The method further includes forming a low-rank matrix to approximate the polynomial coefficient.

    摘要翻译: 一种执行基于投影的多项式拟合的计算机实现方法。 该方法包括生成作为变量的函数的多个采样点。 该方法还包括形成表示多个采样点的多项式模型模板。 根据本发明的实施例,多项式模型模板包括至少一个多项式系数。 该方法还包括形成低秩矩阵以近似多项式系数。

    Statistical optimization and design method for analog and digital circuits
    7.
    发明授权
    Statistical optimization and design method for analog and digital circuits 有权
    模拟和数字电路的统计优化和设计方法

    公开(公告)号:US07669150B2

    公开(公告)日:2010-02-23

    申请号:US11245892

    申请日:2005-10-07

    申请人: Xin Li Larry Pileggi

    发明人: Xin Li Larry Pileggi

    IPC分类号: G06F17/50 G06F9/45

    CPC分类号: G06F17/5036 G06F2217/10

    摘要: A computer implemented method of performing projection based polynomial fitting. The method includes generating a plurality of sampling points as a function of variables. The method also includes forming a polynomial model template representative of the plurality of sampling points. According to embodiments of the present invention, the polynomial model template comprises at least one polynomial coefficient. The method further includes forming a low-rank matrix to approximate the polynomial coefficient.

    摘要翻译: 一种执行基于投影的多项式拟合的计算机实现方法。 该方法包括生成作为变量的函数的多个采样点。 该方法还包括形成表示多个采样点的多项式模型模板。 根据本发明的实施例,多项式模型模板包括至少一个多项式系数。 该方法还包括形成低秩矩阵以近似多项式系数。