公开(公告)号：US4882293A

公开(公告)日：1989-11-21

申请号：US312358

申请日：1989-02-15

申请人： Jorg Naumann ,  Thomas Sharnagl ,  Leo Stroth

发明人： Jorg Naumann ,  Thomas Sharnagl ,  Leo Stroth

IPC分类号： H01L21/82 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/525

CPC分类号： H01L21/76892 ,  H01L21/76886 ,  H01L23/5258 ,  H01L2924/0002

摘要： A method is described of making an electrically programmable integrated circuit which comprises meltable contact bridges (22) between selected connecting points. In the method, firstly in a semiconductor substrate (10) by means of diffusion or ion implantation to obtain desired circuit functions a semiconductor structure with zones (12) of different conductivity type is formed. On the surface of the semiconductor structure a first protective layer (14) is formed in which contact windows (18) to the selected connecting points are then formed. On the surface of the first protective layer (14) and in the contact windoews (18) a through conductive layer (20) is made of a material forming the fusible contact bridges (22). Using a plasma etching method the conductive layer (20) is etched away so that only the contact bridges (22) with an associated connecting end (21) and conductor regions leading from the contact bridges (22) to the connecting points in the contact windows (18) remain. On the remaining conductor regions a second protective layer (24) is formed which is then etched away by means of a plasma etching method except for the regions lying over the contact bridges (22). In the region of the contact windows (18) and on the connecting ends (21) of the contact bridges (22) a connecting metallization (26, 28) is then applied.

公开(公告)号：US5465005A

公开(公告)日：1995-11-07

申请号：US14890

申请日：1993-02-08

申请人： Robert H. Eklund ,  Robert H. Havemann ,  Leo Stroth

发明人： Robert H. Eklund ,  Robert H. Havemann ,  Leo Stroth

IPC分类号： H01L21/02 ,  H01C8/00

CPC分类号： H01L28/20

摘要： An integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

摘要翻译： 本文公开了包括至少一个多晶硅电阻器10的集成电路器件。 形成多晶硅层24，可能在场氧化物12上方。然后掺杂多晶硅层24以获得选定的薄层电阻。 然后在多晶硅层24上形成绝缘层18（例如，氧化物，氮化物或其组合）。图案化和蚀刻绝缘层18以在下面的多晶硅层24中限定电阻体14。 然后对层24进行构图和蚀刻以限定邻接电阻体14的第一和第二电阻头16，同时形成第二电子器件的至少一个多晶硅元件28。 还公开了其它系统和方法。

公开(公告)号：US5236857A

公开(公告)日：1993-08-17

申请号：US785360

申请日：1991-10-30

申请人： Robert H. Eklund ,  Robert H. Havemann ,  Leo Stroth

发明人： Robert H. Eklund ,  Robert H. Havemann ,  Leo Stroth

IPC分类号： H01L21/02

CPC分类号： H01L28/20

摘要： A method of forming an integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

摘要翻译： 本文公开了形成包括至少一个多晶硅电阻器10的集成电路器件的方法。 形成多晶硅层24，可能在场氧化物12上方。然后掺杂多晶硅层24以获得选定的薄层电阻。 然后在多晶硅层24上形成绝缘层18（例如，氧化物，氮化物或其组合）。图案化和蚀刻绝缘层18以在下面的多晶硅层24中限定电阻体14。 然后对层24进行构图和蚀刻以限定邻接电阻体14的第一和第二电阻头16，同时形成第二电子器件的至少一个多晶硅元件28。 还公开了其它系统和方法。

公开(公告)号：US06261915B1

公开(公告)日：2001-07-17

申请号：US08247910

申请日：1994-05-23

申请人： Robert H. Eklund ,  Robert H. Havemann ,  Leo Stroth

发明人： Robert H. Eklund ,  Robert H. Havemann ,  Leo Stroth

IPC分类号： H01L213213

CPC分类号： H01L28/20

摘要： A method of forming an integrated circuit device including at least one polysilicon resistor 10 is disclosed herein. A polysilicon layer 24 is formed, possibly over a field oxide 12. The polysilicon layer 24 is then doped to achieve a selected sheet resistance. An insulating layer 18 (e.g., an oxide, a nitride, or a combination thereof) is then formed over the polysilicon layer 24. The insulating layer 18 is patterned and etched to define a resistor body 14 in the underlying polysilicon layer 24. The polysilicon layer 24 is then patterned and etched to define first and second resistor heads 16 abutting the resistor body 14 while simultaneously at least one polysilicon element 28 of a second electronic device is formed. Other systems and methods are also disclosed.

摘要翻译： 本文公开了一种形成包括至少一个多晶硅电阻器10的集成电路器件的方法。 形成多晶硅层24，可能在场氧化物12上方。然后掺杂多晶硅层24以获得选定的薄层电阻。 然后在多晶硅层24上形成绝缘层18（例如，氧化物，氮化物或其组合）。图案化和蚀刻绝缘层18以在下面的多晶硅层24中限定电阻体14。 然后对层24进行构图和蚀刻以限定邻接电阻体14的第一和第二电阻头16，同时形成第二电子器件的至少一个多晶硅元件28。 还公开了其它系统和方法。