公开(公告)号：US5923193A

公开(公告)日：1999-07-13

申请号：US764608

申请日：1996-12-11

申请人： Peter Bernhardt Bloch ,  Leonard William Cross ,  David Richard Jackson ,  Ali Serhan Oztaskin

发明人： Peter Bernhardt Bloch ,  Leonard William Cross ,  David Richard Jackson ,  Ali Serhan Oztaskin

IPC分类号： H03K5/135

CPC分类号： H04L7/0008 ,  H04L7/0012

摘要： Briefly, in accordance with one embodiment, an integrated circuit includes: electronic circuitry for transferring digital data signals along a digital data signal path between different clock timing domains. The clock timing domains have a common higher frequency source clock. A first clock timing domain clock signal has a relatively fixed phase and a second clock timing domain clock signal has a relatively varying phase. The electronic circuitry includes delay elements in clock signal paths associated with the digital data signal path so that along the digital data signal path, clock signals in different clock timing domains are respectively staggered for a relatively short time compared with a given cycle of the source clock. The electronic circuitry further includes a digital data signal path including a data value retention element to delay the transfer of digital data signals between different clock timing domains at selected times.

摘要翻译： 简而言之，根据一个实施例，集成电路包括：用于沿着不同时钟定时域之间的数字数据信号路径传送数字数据信号的电子电路。 时钟定时域具有共同的较高频率源时钟。 第一时钟定时域时钟信号具有相对固定的相位，并且第二时钟定时域时钟信号具有相对变化的相位。 电子电路包括与数字数据信号路径相关联的时钟信号路径中的延迟元件，使得沿着数字数据信号路径，与源时钟的给定周期相比，不同时钟定时域中的时钟信号分别交错相对短的时间 。 电子电路还包括数字数据信号路径，其包括数据值保持元件，以在选定的时间延迟不同时钟定时域之间的数字数据信号的传送。