Digital baseband carrier recovery circuit
    1.
    发明授权
    Digital baseband carrier recovery circuit 失效
    数字基带载波恢复电路

    公开(公告)号:US4348641A

    公开(公告)日:1982-09-07

    申请号:US110462

    申请日:1980-01-08

    摘要: A recovery loop includes an analog circuit that mixes a fixed frequency signal from a temperature controlled oscillator (20) with an IF input to produce product signals corresponding to the quadrature components of data signals with frequency offset. A digital complex multiplier (32) is responsive to the product signals and to the output of a number controlled oscillator (34) to produce a digital output corresponding to the data signals. The output of the number controlled oscillator (34) is controlled by a digital phase lock loop.

    摘要翻译: 恢复回路包括将来自温度控制振荡器(20)的固定频率信号与IF输入混合的模拟电路,以产生对应于具有频率偏移的数据信号的正交分量的乘积信号。 数字复数乘法器(32)响应于产品信号和数字控制振荡器(34)的输出,以产生对应于数据信号的数字输出。 数字控制振荡器(34)的输出由数字锁相环控制。

    Phase/frequency controlled phase shift keyed signal carrier
reconstruction circuit
    2.
    发明授权
    Phase/frequency controlled phase shift keyed signal carrier reconstruction circuit 失效
    相位/频率控制相移键控信号载波重建电路

    公开(公告)号:US4224575A

    公开(公告)日:1980-09-23

    申请号:US964466

    申请日:1978-11-29

    摘要: A biphase shift keyed modulated carrier is input to an analog delay line having a plurality of sampling taps time spaced along the line. The modulated input carrier is sampled at a rate four times the carrier frequency to produce amplitude samples of the input. The taps of the delay line are divided into two groups comprising alternate tap sets and the amplitude samples of each group are summed for decoding the I and Q channels of a modulated carrier. The summed signal of each of the channels is input to an individual sample and hold circuit which aliases the carrier frequency to baseband. The output of the first sample and hold circuit of each channel is provided to a second sample and hold circuit for the respective channels. The second sample and hold circuit of each channel is clocked at a data rate derived from a bit timing loop. An estimation of the data is produced by each of the second sample and hold circuits with the data produced by the second sample and hold circuit of one channel providing a recovered carrier signal output. Further, the data produced by each of the second sample and hold circuits, after inversion in one line by means of an inverting amplifier, is input to a phase comparator. The output of the phase comparator is filtered and used to drive a voltage controlled oscillator that generates the clock pulses to operate the first sample and hold circuits and also to clock the delay line.

    摘要翻译: 双相移动键控调制载波被输入到具有沿线的间隔时间的多个采样抽头的模拟延迟线。 调制输入载波以载波频率的四倍的速率进行采样,以产生输入的振幅采样。 延迟线的抽头被分成包括备用抽头组的两组,并且将每组的振幅样本相加以对调制载波的I和Q通道进行解码。 每个通道的相加信号被输入到将载波频率平铺到基带的单个采样和保持电路。 每个通道的第一采样和保持电路的输出被提供给用于相应通道的第二采样和保持电路。 每个通道的第二采样和保持电路以从位定时循环得到的数据速率计时。 数据的估计由第二采样和保持电路中的每一个产生,其中由提供恢复的载波信号输出的一个通道的第二采样和保持电路产生的数据产生。 此外,通过反相放大器在一行中反转之后,由第二采样和保持电路中的每一个产生的数据被输入到相位比较器。 相位比较器的输出被滤波并用于驱动压控振荡器,其产生时钟脉冲以操作第一采样和保持电路,并且还对延迟线进行时钟。