公开(公告)号：US08106688B2

公开(公告)日：2012-01-31

申请号：US12620689

申请日：2009-11-18

申请人： Haitao Huang ,  Min Zhang ,  Liding Yin

发明人： Haitao Huang ,  Min Zhang ,  Liding Yin

IPC分类号： H03K7/00

CPC分类号： H03K17/22 ,  H03K17/24

摘要： A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.

摘要翻译： 上电复位电路包括第一电路和第二电路。 第一电路包括具有由低电压电源VDD_L控制的栅极的第一NMOS晶体管，连接在第一NMOS晶体管的源极和低于VDD_L的电压源VSS之间的电阻器，以及一个或多个二极管，串联连接在 高压电源VDD_H和第一NMOS晶体管的漏极。 第二电路包括具有连接到VDD_L的源极的第一PMOS晶体管，具有连接到第一PMOS晶体管的漏极的源极的第二PMOS晶体管，连接在第二PMOS晶体管的漏极和VSS之间的第二NMOS晶体管，以及反相器 被配置为响应于高压电源VDD_H和低电压电源VDD_L的电源接通而输出信号。

公开(公告)号：US20110115533A1

公开(公告)日：2011-05-19

申请号：US12620689

申请日：2009-11-18

申请人： Haitao Huang ,  Min Zhang ,  Liding Yin

发明人： Haitao Huang ,  Min Zhang ,  Liding Yin

IPC分类号： H03L7/00

CPC分类号： H03K17/22 ,  H03K17/24

摘要： A power-on reset circuit includes a first circuit and a second circuit. The first circuit include a first NMOS transistor having a gate controlled by a low voltage supply VDD_L, a resistor connected between the source of the first NMOS transistor and a voltage supply VSS that is lower than VDD_L, and one or more diodes serially connected between a high voltage supply VDD_H and the drain of the first NMOS transistor. The second circuit includes a first PMOS transistor having a source connected to VDD_L, a second PMOS transistor having a source connected to the drain of first PMOS transistor, a second NMOS transistor connected between the drain of the second PMOS transistor and VSS, and an inverter configured to output a signal in response to the power on of the high voltage supply VDD_H and the low voltage supply VDD_L.

摘要翻译： 上电复位电路包括第一电路和第二电路。 第一电路包括具有由低电压电源VDD_L控制的栅极的第一NMOS晶体管，连接在第一NMOS晶体管的源极和低于VDD_L的电压源VSS之间的电阻器，以及一个或多个二极管，串联连接在 高压电源VDD_H和第一NMOS晶体管的漏极。 第二电路包括具有连接到VDD_L的源极的第一PMOS晶体管，具有连接到第一PMOS晶体管的漏极的源极的第二PMOS晶体管，连接在第二PMOS晶体管的漏极和VSS之间的第二NMOS晶体管，以及反相器 被配置为响应于高压电源VDD_H和低电压电源VDD_L的电源接通而输出信号。