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    Post silicide testing for replacement high-k metal gate technologies
    1.
    发明授权
    Post silicide testing for replacement high-k metal gate technologies 有权
    后置硅化物测试替代高k金属栅极技术

    公开(公告)号：US08610451B2

    公开(公告)日：2013-12-17

    申请号：US12946875

    申请日：2010-11-16

    申请人： Ishtiaq Ahsan ,  David M. Fried ,  Lidor Goren ,  Jiun-Hsin Liao

    发明人： Ishtiaq Ahsan ,  David M. Fried ,  Lidor Goren ,  Jiun-Hsin Liao

    IPC分类号： G01R31/26

    CPC分类号： H01L22/34 ,  G01R31/2621

    摘要： A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines.

    摘要翻译： 用于测试IC器件中的晶体管栅极结构的测试结构包括形成在IC器件的有效区域上的一个或多个探针焊盘; 一个或多个第一导电线形成在所述IC器件的有源区，与所述一个或多个探针焊盘电接触; 形成在所述IC器件的栅极导体级的一个或多个第二导线，与所述一个或多个第一导线电接触; 以及要与所述一个或多个第二导线电接触测试的栅电极结构; 其中所述一个或多个第二导电线与所述一个或多个第一导电线之间的电接触由设置在所述一个或多个第二导电线与所述一个或多个第一导电线之间的栅极电介质材料的局部介电击穿来促进。

    Method for creating a parameterized cell library dual-layered rule system for rapid technology migration
    2.
    发明授权
    Method for creating a parameterized cell library dual-layered rule system for rapid technology migration 失效
    用于创建用于快速技术迁移的参数化单元库双层规则系统的方法

    公开(公告)号：US07512911B1

    公开(公告)日：2009-03-31

    申请号：US12204074

    申请日：2008-09-04

    申请人： Lidor Goren ,  Alex Raphayevich ,  Tamara Aviv

    发明人： Lidor Goren ,  Alex Raphayevich ,  Tamara Aviv

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A parameterized cell library including variable names corresponding to characteristics of components on an integrated circuit design may reference variable values stored in a first rule layer via internally used rule names stored in a second rule layer. The first and second rule layers may be stored as association tables. The first rule layer may store rule names corresponding to one or more geometric constraints of the integrated circuit design, and the rule names may directly reference variable values derived from a technology manual. The second rule layer may store internally used rule names corresponding to rule names stored in the first rule layer, and the internally used rule names may reference the rule names stored in the first rule layer.

    摘要翻译： 包括对应于集成电路设计上的组件的特征的变量名称的参数化单元库可以经由存储在第二规则层中的内部使用的规则名称来引用存储在第一规则层中的变量值。 第一和第二规则层可以被存储为关联表。 第一规则层可以存储对应于集成电路设计的一个或多个几何约束的规则名称，并且规则名称可以直接引用从技术手册导出的变量值。 第二规则层可以存储对应于存储在第一规则层中的规则名称的内部使用的规则名称，并且内部使用的规则名称可以引用存储在第一规则层中的规则名称。

    Method and system for modeling wiring routing in a circuit design
    4.
    发明申请
    Method and system for modeling wiring routing in a circuit design 失效
    在电路设计中对布线布线进行建模的方法和系统

    公开(公告)号：US20070067750A1

    公开(公告)日：2007-03-22

    申请号：US11232747

    申请日：2005-09-22

    申请人： Niv Amit ,  Ronit Bustin ,  Lidor Goren ,  Omer Heymann ,  Moshe Leibowitz ,  Gil Noy ,  Alex Raphayevich ,  Maya Speiser

    发明人： Niv Amit ,  Ronit Bustin ,  Lidor Goren ,  Omer Heymann ,  Moshe Leibowitz ,  Gil Noy ,  Alex Raphayevich ,  Maya Speiser

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “Π”-type filter arrangement, wherein n=1, 2, 3, . . . , }. Several length ranges may be predefined to associate each segment, or path, with a particular type of wire model object.

    摘要翻译： 本发明是一种在电路设计中对线路布线进行建模的方法和系统。 根据一些实施例，线模型对象（“WMO”）可以以“WMO-per-segment”为基础插入到布线路由中。 根据一些其他实施例，可以将线模型对象插入到每组连续段的布线路由中。 整个布线布线几何可以构成一个组，并且可以基于路由几何中最长的路径将线模型对象插入在源点和目标点之间。 可以基于以下因素的任何组合来选择插入规则：段长度，总路径长度，相邻段之间的间隔，金属丝和线宽度。 线模型对象可以从由以下组成的组中选择：{“C”; 一个“RC”安排; 'n'次“Pi”型滤波器布置，其中n = 1,2,3。 。 。 ，}。 可以预定义几个长度范围以将每个段或路径与特定类型的线模型对象相关联。

    POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES
    7.
    发明申请
    POST SILICIDE TESTING FOR REPLACEMENT HIGH-K METAL GATE TECHNOLOGIES 有权
    用于更换高K金属门技术的硅胶测试

    公开(公告)号：US20120119778A1

    公开(公告)日：2012-05-17

    申请号：US12946875

    申请日：2010-11-16

    申请人： Ishtiaq Ahsan ,  David M. Fried ,  Lidor Goren ,  Jiun-Hsin Liao

    发明人： Ishtiaq Ahsan ,  David M. Fried ,  Lidor Goren ,  Jiun-Hsin Liao

    IPC分类号： G01R31/26 ,  H01L23/58 ,  H01L21/66

    CPC分类号： H01L22/34 ,  G01R31/2621

    摘要： A test structure for testing transistor gate structures in an IC device includes one or more probe pads formed at an active area of the IC device; one or more first conductive lines formed at the active area of the IC device, in electrical contact with the one or more probe pads; one or more second conductive lines formed at a gate conductor level of the IC device, in electrical contact with the one or more first conductive lines; and a gate electrode structure to be tested in electrical contact with the one or more second conductive lines; wherein the electrical contact between the one or more second conductive lines and the one or more first conductive lines is facilitated by a localized dielectric breakdown of a gate dielectric material disposed between the one or more second conductive lines and the one or more first conductive lines.

    摘要翻译： 用于测试IC器件中的晶体管栅极结构的测试结构包括形成在IC器件的有效区域上的一个或多个探针焊盘; 一个或多个第一导电线形成在所述IC器件的有源区，与所述一个或多个探针焊盘电接触; 形成在所述IC器件的栅极导体级的一个或多个第二导线，与所述一个或多个第一导线电接触; 以及要与所述一个或多个第二导线电接触测试的栅电极结构; 其中所述一个或多个第二导电线与所述一个或多个第一导电线之间的电接触由设置在所述一个或多个第二导电线与所述一个或多个第一导电线之间的栅极电介质材料的局部介电击穿来促进。

    Method and system for modeling wiring routing in a circuit design
    9.
    发明授权
    Method and system for modeling wiring routing in a circuit design 失效
    在电路设计中对布线布线进行建模的方法和系统

    公开(公告)号：US07318212B2

    公开(公告)日：2008-01-08

    申请号：US11232747

    申请日：2005-09-22

    申请人： Niv Amit ,  Ronit Bustin ,  Lidor Goren ,  Omer Heymann ,  Moshe Leibowitz ,  Gil Noy ,  Alex Raphayevich ,  Maya Speiser

    发明人： Niv Amit ,  Ronit Bustin ,  Lidor Goren ,  Omer Heymann ,  Moshe Leibowitz ,  Gil Noy ,  Alex Raphayevich ,  Maya Speiser

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036

    摘要： The present invention is a method and system for modeling wiring routing in circuit design. According to some embodiments, the wire model objects (“WMO”) may be inserted into the wiring routing on a ‘WMO-per-segment’ basis. According to some other embodiments, the wire model objects may be inserted into the wiring routing per groups of sequential segments. The entire wiring routing geometry may constitutes one group, and a wire model object may be inserted between the source point(s) and the target points based on the longest path in the routing geometry. An insertion rule may be selected based on any combination of the following factors: segment length, total path length, spacing between adjacent segments, wire metal and wire width. A wire model object may be selected from a group consisting of: {“C”; one “RC” arrangement; ‘n’ times “Π”-type filter arrangement, wherein n=1, 2, 3, . . . , }. Several length ranges may be predefined to associate each segment, or path, with a particular type of wire model object.

    摘要翻译： 本发明是一种在电路设计中对线路布线进行建模的方法和系统。 根据一些实施例，线模型对象（“WMO”）可以以“WMO-per-segment”为基础插入到布线路由中。 根据一些其他实施例，可以将线模型对象插入到每组连续段的布线路由中。 整个布线布线几何可以构成一个组，并且可以基于路由几何中最长的路径将线模型对象插入在源点和目标点之间。 可以基于以下因素的任何组合来选择插入规则：段长度，总路径长度，相邻段之间的间隔，金属丝和线宽度。 线模型对象可以从由以下组成的组中选择：{“C”; 一个“RC”安排; 'n'次“Pi”型滤波器布置，其中n = 1,2,3。 。 。 ，}。 可以预定义几个长度范围以将每个段或路径与特定类型的线模型对象相关联。