High Speed Parallel Procesing Digita Path for SAR ADC
    3.
    发明申请
    High Speed Parallel Procesing Digita Path for SAR ADC 有权
    SAR ADC的高速并行处理数字通路

    公开(公告)号:US20090102694A1

    公开(公告)日:2009-04-23

    申请号:US12254678

    申请日:2008-10-20

    IPC分类号: H03M1/34

    摘要: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

    摘要翻译: 公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器(ADC)的模拟数字转换器。 在一个示例实施例中,ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。 比较器耦合到开关电容器DAC。 逐次逼近寄存器(SAR)耦合到比较器。 多个逻辑块耦合到SAR。 多个温度测量编码器耦合到相关联的多个逻辑块。 多个MUX耦合到相关联的多个温度测量编码器和比较器,其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。

    Parallel digital processing for reducing delay in SAR ADC logic
    4.
    发明授权
    Parallel digital processing for reducing delay in SAR ADC logic 有权
    用于减少SAR ADC逻辑延迟的并行数字处理

    公开(公告)号:US07439898B1

    公开(公告)日:2008-10-21

    申请号:US11755761

    申请日:2007-05-31

    IPC分类号: H03M1/34

    摘要: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

    摘要翻译: 公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器(ADC)的模拟数字转换器。 在一个示例实施例中,ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。 比较器耦合到开关电容器DAC。 逐次逼近寄存器(SAR)耦合到比较器。 多个逻辑块耦合到SAR。 多个温度测量编码器耦合到相关联的多个逻辑块。 多个MUX耦合到相关联的多个温度测量编码器和比较器,其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。

    High speed parallel procesing digita path for SAR ADC
    5.
    发明授权
    High speed parallel procesing digita path for SAR ADC 有权
    SAR ADC的高速并行处理数字通路

    公开(公告)号:US07839319B2

    公开(公告)日:2010-11-23

    申请号:US12254678

    申请日:2008-10-20

    IPC分类号: H03M1/34

    摘要: The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.

    摘要翻译: 公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器(ADC)的模拟数字转换器。 在一个示例实施例中,ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。 比较器耦合到开关电容器DAC。 逐次逼近寄存器(SAR)耦合到比较器。 多个逻辑块耦合到SAR。 多个温度测量编码器耦合到相关联的多个逻辑块。 多个MUX耦合到相关联的多个温度测量编码器和比较器,其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。