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    Successive approximation register analog to digital converter device and signal conversion method
    1.
    发明授权
    Successive approximation register analog to digital converter device and signal conversion method 有权

    公开(公告)号：US12107597B2

    公开(公告)日：2024-10-01

    申请号：US17857621

    申请日：2022-07-05

    Applicant: REALTEK SEMICONDUCTOR CORPORATION

    Inventor： Shih-Hsiung Huang ,  Wei-Cian Hong ,  Sheng-Yen Shih

    IPC: H03M1/12 ,  H03M1/46

    CPC classification number: H03M1/468 ,  H03M1/1245

    Abstract: A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.

    Successive approximation register analog-to-digital converter with embedded filtering
    2.
    发明授权
    Successive approximation register analog-to-digital converter with embedded filtering 有权

    公开(公告)号：US11888497B2

    公开(公告)日：2024-01-30

    申请号：US17893076

    申请日：2022-08-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Debapriya Sahu ,  Pranav Sinha ,  Meghna Agrawal

    IPC: H03M1/06 ,  H03M1/46 ,  H03M1/18

    CPC classification number: H03M1/462 ,  H03M1/0626 ,  H03M1/182 ,  H03M1/468

    Abstract: An analog-to-digital converter (ADC) includes a switched capacitor circuit, a comparator, and a control circuit. The switched capacitor circuit has a switch control input and an output, and includes switches coupled to the switch control input and coupled to capacitors. The comparator has an input coupled to the output of the switched capacitor circuit and has an output. The control circuit has a switch control output coupled to the switch control input, has an input coupled to the output of the comparator, and provides switch control signals at the switch control output. Responsive to the switch control signals, the switched capacitor circuit provides an output signal to the comparator that is based on a sample of an analog input signal acquired in a sample acquisition cycle and based on a digital sample value output by the ADC prior to the sample acquisition cycle.

    Differential Subrange ADC for Image Sensor
    4.
    发明公开
    Differential Subrange ADC for Image Sensor 审中-公开

    公开(公告)号：US20230179889A1

    公开(公告)日：2023-06-08

    申请号：US17540434

    申请日：2021-12-02

    Applicant: OmniVision Technologies,Inc.

    Inventor： Chao-Fang Tsai ,  Zheng Yang ,  Chun-Hsiang Chang

    IPC: H04N5/3745 ,  H03M1/46 ,  H03M1/56 ,  H04N5/378

    CPC classification number: H04N5/37455 ,  H03M1/468 ,  H03M1/462 ,  H03M1/56 ,  H04N5/378

    Abstract: A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.

    Dual Reset Branch Analog-to-Digital Conversion
    5.
    发明申请
    Dual Reset Branch Analog-to-Digital Conversion 审中-公开

    公开(公告)号：US20190238148A1

    公开(公告)日：2019-08-01

    申请号：US16378532

    申请日：2019-04-08

    Applicant: Forza Silicon Corporation

    Inventor： Daniel Van Blerkom

    IPC: H03M1/12 ,  H03M1/46 ,  H03M1/40 ,  H03M1/38

    CPC classification number: H03M1/1215 ,  H03M1/1205 ,  H03M1/122 ,  H03M1/123 ,  H03M1/38 ,  H03M1/40 ,  H03M1/403 ,  H03M1/46 ,  H03M1/462 ,  H03M1/464 ,  H03M1/466 ,  H03M1/468

    Abstract: Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

    ANALOG-TO-DIGITAL CONVERTER
    6.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER 审中-公开

    公开(公告)号：US20190222222A1

    公开(公告)日：2019-07-18

    申请号：US16261945

    申请日：2019-01-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Shridhar MORE ,  Rahul Vijay KULKARNI

    IPC: H03M1/46

    CPC classification number: H03M1/462 ,  H03M1/468

    Abstract: An analog-to-digital converter includes an input terminal, a digital-to-analog converter, a comparator, and successive approximation circuitry. The input terminal is configured to receive a multi-bit digital threshold value from circuitry external to the analog-to-digital converter. The successive approximation circuitry is coupled to the comparator and the digital-to-analog converter. The successive approximation circuitry is configured to operate in a comparison mode and a conversion mode, and to provide the multi-bit digital threshold value to the digital-to-analog converter while operating in the comparison mode. The comparator is coupled to the digital-to-analog converter and the successive approximation circuity. The comparator is configured to output a signal that indicates whether an analog input signal exceeds an analog threshold signal corresponding to the multi-bit digital threshold value.

    ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND METHOD
    8.
    发明申请
    ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND METHOD 审中-公开

    公开(公告)号：US20190058486A1

    公开(公告)日：2019-02-21

    申请号：US16168774

    申请日：2018-10-23

    Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.

    Inventor： Shuo FAN

    IPC: H03M1/46 ,  H03M1/12

    CPC classification number: H03M1/466 ,  H03M1/002 ,  H03M1/1245 ,  H03M1/129 ,  H03M1/468

    Abstract: An analog-to-digital conversion circuit and method are provided. At a sampling stage, the first capacitor array connects lower electrode plates of N capacitors to a first input voltage, connect lower electrode plates of the other capacitors to a common-mode voltage, and connect upper electrode plates of all the capacitors to the common-mode voltage to sample the first input voltage; in an ith conversion at a conversion stage, the logic circuit controls, the lower electrode plate of an ith capacitor to connect to a reference voltage or a ground voltage, a first comparison voltage output by the first capacitor array approximates a second comparison voltage; and the comparator stores a comparison result between the first and the second comparison voltage to an i+1th flag bit in the logic circuit, and analog-to-digital conversion is completed when i+1 is equal to the total number of capacitors in the first capacitor array.

    CAPACITIVE SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
    9.
    发明申请
    CAPACITIVE SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER 审中-公开

    公开(公告)号：US20190020351A1

    公开(公告)日：2019-01-17

    申请号：US16119739

    申请日：2018-08-31

    Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.

    Inventor： Shuo FAN

    IPC: H03M1/46 ,  H03M1/80

    CPC classification number: H03M1/468 ,  H03M1/462 ,  H03M1/804

    Abstract: A capacitive successive approximation analog-to-digital converter is provided, where the capacitive successive approximation analog-to-digital converter includes a first capacitor array including N first capacitors; a second capacitor array including N second capacitors; a voltage generation circuit configured to generate a common mode voltage, a reference voltage, a first voltage and a second voltage; a first switch, a second switch, N third switches and N fourth switches; a comparator including a first input end, a second input end and an output end, where upper plates of the N first capacitors are connected to the first input end and upper plates of the N second capacitors are connected to the second input end; and a successive approximation logic controller connected to the output end of the comparator. The capacitive successive approximation analog-to-digital converter in the above technical solution can use 2N capacitors to implement outputting an N-bit binary code.

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