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1.发明授权Synchronous DRAM having test mode in which automatic refresh is performed according to external address and automatic refresh method 失效具有根据外部地址和自动刷新方法执行自动刷新的测试模式的同步DRAM公开(公告)号：US06633504B1
公开(公告)日：2003-10-14
申请号：US09517396
申请日：2000-03-02
申请人： Mahn-joong Lee , Man-sik Choi
发明人： Mahn-joong Lee , Man-sik Choi
IPC分类号： G11C700
CPC分类号： G11C7/1072 , G11C11/401 , G11C11/406 , G11C29/24
摘要： A synchronous DRAM and method are provided in which main cells and spare cells are accessed by an external address during automatic refresh of a test mode. In the synchronous DRAM, a mode register setting circuit receives an external signal in response to a plurality of control signals to generate a mode register setting signal, during an automatic refresh operation in a test mode. An address selector selects and outputs an external address to the memory cell array, in response to the activation of the mode register set signal, during the automatic refresh operation in the test mode. The address selector selects and outputs an internal address to the memory cell array, in response to the deactivation of the mode register set signal, during an automatic refresh operation in a normal mode. Therefore, the main cells and the spare cells in the memory cell array are sequentially accessed and refreshed by the external address during the automatic refresh operation in the test mode.
摘要翻译： 提供了同步DRAM和方法，其中主单元和备用单元在测试模式的自动刷新期间被外部地址访问。 在同步DRAM中，模式寄存器设置电路在测试模式下的自动刷新操作期间响应于多个控制信号接收外部信号以产生模式寄存器设置信号。 在测试模式的自动刷新操作期间，地址选择器响应于模式寄存器设置信号的激活，选择并输出到存储单元阵列的外部地址。 在正常模式下的自动刷新操作期间，地址选择器响应于模式寄存器设置信号的去激活而选择并输出到存储单元阵列的内部地址。 因此，在测试模式下的自动刷新操作期间，存储单元阵列中的主单元和备用单元被外部地址顺序访问和刷新。
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2.发明授权Parallel bit test circuit in semiconductor memory device and associated method 失效半导体存储器件中的并行位测试电路及相关方法公开(公告)号：US07496808B2
公开(公告)日：2009-02-24
申请号：US11149907
申请日：2005-06-10
申请人： Young-Suk Kim , Mahn-Joong Lee
发明人： Young-Suk Kim , Mahn-Joong Lee
IPC分类号： G11C29/00
摘要： An embodiment is a circuit including 2n−1 first comparators to generate a first result by comparing data from at least two of 2n memory cells to which test pattern data are written. 2n−1 first switching circuits provide the first result or a disable signal responsive to a first switching signal. And 2n−2 second comparators generate a second result by comparing signals output from some of the 2n−1 first switching circuits. N may be a natural number greater than or equal to three.
摘要翻译： 一个实施例是包括2n-1个第一比较器的电路，用于通过比较从2n个存储器单元中至少两个写入测试图形数据的数据来产生第一结果。 2n-1个第一开关电路提供响应于第一开关信号的第一结果或禁用信号。 并且2n-2个第二比较器通过比较从2n-1个第一开关电路中的一些输出的信号来产生第二结果。 N可以是大于或等于三的自然数。
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3.发明申请Parallel bit test circuit in semiconductor memory device and associated method 失效半导体存储器件中的并行位测试电路及相关方法公开(公告)号：US20050289412A1
公开(公告)日：2005-12-29
申请号：US11149907
申请日：2005-06-10
申请人： Young-Suk Kim , Mahn-Joong Lee
发明人： Young-Suk Kim , Mahn-Joong Lee
摘要： An embodiment is a circuit including 2n-1 first comparators to generate a first result by comparing data from at least two of 2n memory cells to which test pattern data are written. 2n-1 first switching circuits provide the first result or a disable signal responsive to a first switching signal. And 2n-2 second comparators generate a second result by comparing signals output from some of the 2n-1 first switching circuits. N may be a natural number greater than or equal to three.
摘要翻译： 一个实施例是包括2个n-1个第一比较器的电路，用于通过比较写入测试图形数据的2个个存储器单元中的至少两个的数据来产生第一个结果 。 第一开关电路提供响应于第一开关信号的第一结果或禁用信号。 而且，第二比较器通过比较从2n-1-n个第一开关电路中的一些输出的信号产生第二结果。 N可以是大于或等于三的自然数。
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