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公开(公告)号：US08614143B2
公开(公告)日：2013-12-24
申请号：US12327336
申请日：2008-12-03
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76816 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.
摘要翻译： 本发明的一个实施例涉及一种配置成利用单个光刻和蚀刻工艺形成金属化和通孔级的光刻掩模。 更具体地，包括掩模通孔形状和一个或多个金属线形状的光刻掩模被配置为产生晶片上金属线和通孔级。 掩模通孔形状对应于具有第一临界尺寸（CD）的经晶片上的光刻胶通孔开口。 一个或多个掩模线形状对应于分别具有第二CD的一个或多个晶片上的光致抗蚀剂丝线开口。 第一CD大于第二CD，从而为由光致抗蚀剂经由开口暴露的ILD提供比通过一个或多个光致抗蚀剂线开口暴露的ILD更大的垂直蚀刻速率。 CD中的这种差异导致在金属线水平面垂直延伸的通孔，从而与底层金属物理接触。
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2.发明授权In line test circuit and method for determining interconnect electrical properties and integrated circuit incorporating the same 有权用于确定互连电性能的在线测试电路和方法及其结合的集成电路公开(公告)号：US07855090B2
公开(公告)日：2010-12-21
申请号：US12850415
申请日：2010-08-04
IPC分类号： H01R31/26
CPC分类号： G01R31/31717
摘要： A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.
摘要翻译： 用于确定集成电路（IC）的底层互连层和上覆互连层的电性能的测试电路及其方法，以及包含测试电路或方法的IC。 在一个实施例中，测试电路包括具有环路和阶段的门链。 在一个实施例中，该阶段包括：（1）底层互连层中的底层测试段，（2）上覆互连层中的覆盖测试段和（3）逻辑电路在形成底层互连层之后并且在形成之前活动 的上层互连层，以将下面的测试段放置在环路径中，并且在形成上覆互连层之后进一步激活，以将覆盖的测试段替换为环路径中的底层测试段。
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公开(公告)号：US08379433B2
公开(公告)日：2013-02-19
申请号：US12882355
申请日：2010-09-15
IPC分类号： G11C11/24
CPC分类号： G11C11/403
摘要： A 3T DRAM cell includes a first transistor having a first control element connected as a storage node and a second transistor connected between the first transistor and a read bit line having a second control element connected to a read word line. The 3T DRAM cell also includes a third transistor connected between the storage node and a write bit line having a third control element connected to a write word line. Additionally, the DRAM cell includes a supplemental capacitance connected to the storage node and configured to extend a refresh interval of the 3T DRAM cell. A method of operating an integrated circuit having a 3T DRAM cell includes providing a memory state on a storage node of the 3T DRAM cell and extending a refresh interval of the memory state with a supplemental capacitance added to the storage node.
摘要翻译： 3T DRAM单元包括具有作为存储节点连接的第一控制元件的第一晶体管和连接在第一晶体管和读位线之间的第二晶体管，其具有连接到读字线的第二控制元件。 3T DRAM单元还包括连接在存储节点和写入位线之间的第三晶体管，其具有连接到写入字线的第三控制元件。 另外，DRAM单元包括连接到存储节点并被配置为扩展3T DRAM单元的刷新间隔的补充电容。 操作具有3T DRAM单元的集成电路的方法包括在3T DRAM单元的存储节点上提供存储器状态，并且通过添加到存储节点的补充电容来扩展存储器状态的刷新间隔。
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4.发明申请公开(公告)号：US20100297793A1
公开(公告)日：2010-11-25
申请号：US12850415
申请日：2010-08-04
IPC分类号： H01L21/66
CPC分类号： G01R31/31717
摘要： A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.
摘要翻译： 用于确定集成电路（IC）的底层互连层和上覆互连层的电性能的测试电路及其方法，以及包含测试电路或方法的IC。 在一个实施例中，测试电路包括具有环路和阶段的门链。 在一个实施例中，该阶段包括：（1）底层互连层中的底层测试段，（2）上覆互连层中的覆盖测试段和（3）逻辑电路在形成下面的互连层之后并且在形成前 的上层互连层，以将下面的测试段放置在环路径中，并且在形成上覆互连层之后进一步激活，以将覆盖的测试段替换为环路径中的底层测试段。
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5.发明授权In-line test circuit and method for determining interconnect electrical properties and integrated circuit incorporating the same 有权用于确定互连电性能的在线测试电路和方法以及包括其的集成电路公开(公告)号：US07786475B2
公开(公告)日：2010-08-31
申请号：US11383853
申请日：2006-05-17
IPC分类号： H01L29/10
CPC分类号： G01R31/31717
摘要： A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.
摘要翻译： 用于确定集成电路（IC）的底层互连层和上覆互连层的电性能的测试电路及其方法，以及包含测试电路或方法的IC。 在一个实施例中，测试电路包括具有环路和阶段的门链。 在一个实施例中，该阶段包括：（1）底层互连层中的底层测试段，（2）上覆互连层中的覆盖测试段和（3）逻辑电路在形成下面的互连层之后并且在形成前 的上层互连层，以将下面的测试段放置在环路径中，并且在形成上覆互连层之后进一步激活，以将覆盖的测试段替换为环路径中的底层测试段。
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公开(公告)号：US20100136781A1
公开(公告)日：2010-06-03
申请号：US12327336
申请日：2008-12-03
IPC分类号： H01L21/768 , G03F1/00
CPC分类号： H01L21/76807 , H01L21/76816 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention relates to a photolithography mask configured to form a metallization and via level utilizing a single lithography and etch process. More particularly, a photolithography mask comprising a mask via shape and one or more metal wire shapes is configured to produce both on-wafer metal lines and via levels. The mask via shape corresponds to an on-wafer photoresist via opening having a first critical dimension (CD). The one or more mask wire shapes correspond to one or more on-wafer photoresist wire openings respectively having a second CD. The first CD is larger than the second CD thereby providing a greater vertical etch rate for ILD exposed by the photoresist via opening than for ILD exposed by the one or more photoresist wire openings. This difference in CD results in a via extending vertically below the metal wire level, thereby making physical contact with underlying metal.
摘要翻译： 本发明的一个实施例涉及一种配置成利用单个光刻和蚀刻工艺形成金属化和通孔级的光刻掩模。 更具体地，包括掩模通孔形状和一个或多个金属线形状的光刻掩模被配置为产生晶片上金属线和通孔级。 掩模通孔形状对应于具有第一临界尺寸（CD）的经晶片上的光刻胶通孔开口。 一个或多个掩模线形状对应于分别具有第二CD的一个或多个晶片上的光致抗蚀剂丝线开口。 第一CD大于第二CD，从而为由光致抗蚀剂经由开口曝光的ILD提供比通过一个或多个光致抗蚀剂线开口暴露的ILD更大的垂直蚀刻速率。 CD中的这种差异导致在金属线水平面垂直延伸的通孔，从而与底层金属物理接触。
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7.发明申请公开(公告)号：US20070269912A1
公开(公告)日：2007-11-22
申请号：US11383853
申请日：2006-05-17
IPC分类号： H01L21/66
CPC分类号： G01R31/31717
摘要： A test circuit for, and method of, determining electrical properties of an underlying interconnect layer and an overlying interconnect layer of an integrated circuit (IC) and an IC incorporating the test circuit or the method. In one embodiment, the test circuit includes a gate chain having a ring path and a stage. In one embodiment, the stage includes: (1) a underlying test segment in the underlying interconnect layer, (2) a overlying test segment in the overlying interconnect layer and (3) logic circuitry activatible after formation of the underlying interconnect layer and before formation of the overlying interconnect layer to place the underlying test segment in the ring path and further activatible after the formation of the overlying interconnect layer to substitute the overlying test segment for the underlying test segment in the ring path.
摘要翻译： 用于确定集成电路（IC）的底层互连层和上覆互连层的电性能的测试电路及其方法，以及包含测试电路或方法的IC。 在一个实施例中，测试电路包括具有环路和阶段的门链。 在一个实施例中，该阶段包括：（1）底层互连层中的底层测试段，（2）上覆互连层中的覆盖测试段和（3）逻辑电路在形成下面的互连层之后并且在形成前 的上层互连层，以将下面的测试段放置在环路径中，并且在形成上覆互连层之后进一步激活，以将覆盖的测试段替换为环路径中的底层测试段。
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