公开(公告)号：US6148322A

公开(公告)日：2000-11-14

申请号：US341813

申请日：1994-11-18

Applicant: Manfred Sand ,  Georg Trummer

Inventor： Manfred Sand ,  Georg Trummer

IPC: G06F9/48 ,  G06F9/46

CPC classification number: G06F9/4837

Abstract: The present invention provides a processing unit with an improved ability to coordinate the execution of multiple tasks with varying priorities. Tasks to be executed are assigned both a request condition and a terminating condition, with the processing unit initiating execution of the task with the highest priority whose request condition is satisfied. In general, the processing unit terminates an executing task once the terminating condition of that task is satisfied, and then initiates execution of the next highest-priority task with a satisfied request condition. However, the processing unit may abort execution of a task (other than the highest-priority task) if the request condition of a higher-priority task becomes satisfied. Moreover, the processing unit ensures the highest-priority task does not monopolize system resources by tracking the elapsed execution time and terminating the highest-priority task if this elapsed time exceeds a predetermined maximum, in which case the processing unit initiates execution of the next highest priority task with a satisfied request condition.

Abstract translation: 本发明提供一种处理单元，其具有改进的能力，以协调具有不同优先级的多个任务的执行。 要执行的任务被分配请求条件和终止条件，处理单元开始执行请求条件满足的最高优先级的任务。 通常，一旦满足该任务的终止条件，则处理单元终止执行任务，然后以满足的请求条件开始执行下一个最高优先级任务。 然而，如果较高优先级任务的请求条件满足，则处理单元可以中止任务（除最高优先级任务之外）的执行。 此外，处理单元通过跟踪经过的执行时间并终止最高优先级的任务，如果该经过时间超过预定的最大值，则确保最高优先级的任务不会垄断系统资源，在这种情况下，处理单元启动下一个最高优先级的执行 具有满足请求条件的优先任务。

公开(公告)号：US5600671A

公开(公告)日：1997-02-04

申请号：US439556

申请日：1995-05-11

Applicant: Jurgen Maul ,  Manfred Sand ,  Georg Trummer ,  Werner Schlieker

Inventor： Jurgen Maul ,  Manfred Sand ,  Georg Trummer ,  Werner Schlieker

IPC: G06F13/00 ,  G05B19/042 ,  H04L12/403 ,  H04B1/38

CPC classification number: G05B19/0423 ,  H04L12/403

Abstract: A modular programmable controller, comprised of a central processing unit and peripheral units, has a serial bus system in the form of a shift register. The total length of the shift register is equal to the sum of the individual register lengths of the bus interface connections of the peripheral units. The individual register lengths of the bus interface connections are dependent upon command and peripheral units. The individual register lengths amount to between 0 and 40 bits. This results in an exceptionally efficient exchange of information between the central processing unit and peripheral units.

Abstract translation: 由中央处理单元和外围单元组成的模块化可编程控制器具有移位寄存器形式的串行总线系统。 移位寄存器的总长度等于外围单元的总线接口连接的各个寄存器长度之和。 总线接口连接的各个寄存器长度取决于命令和外设。 单个寄存器长度在0到40位之间。 这导致中央处理单元和外围单元之间的信息交换非常有效。